Texas Instruments TMS320C28x Reference Manual page 676

R
product shift mode (PM) bits: A 3-bit field in status register ST0 that en-
ables you to select one of eight product shift modes. The product shift
mode determines whether or how the P register value is shifted before
being used by an instruction. You have the choices of a left shift by 1 bit,
no shift, or a right shift by N, where N is a number from 1 to 6.
program address bus (PAB): The bus that carries addresses for reads and
writes from program space.
program address generation logic: This logic generates the addresses
used to fetch instructions or data from program memory and places each
address on the program address bus (PAB).
program control logic: This logic stores a queue of instructions that have
been fetched from program memory by way of the program-read bus
(PRDB). It also decodes these instructions and passes commands and
constant data to other parts of the CPU.
program counter (PC): When the pipeline is full, the 22-bit PC always
points to the instruction that is currently being processed—the instruction
that has just reached the decode 2 phase of the pipeline.
program-flow discontinuity: A branching to a nonsequential address
caused by a branch, a call, an interrupt, a return, or the repetition of an
instruction.
program-read data bus (PRDB): The bus that carries instructions or data
during reads from program space.
R1 phase: See read 1 (R1) phase.
R2 phase: See read 2 (R2) phase.
read 1 (R1) phase: The fifth of eight pipeline phases an instruction passes
through. In this phase, if data is to be read from memory, the CPU drives
the address(es) on the appropriate address bus(es). See also pipeline
phases.
read 2 (R2) phase: The sixth of eight pipeline phases an instruction passes
through. In this phase, data addressed in the read 1 phase is fetched
from memory. See also pipeline phases.
Glossary
Glossary G-17