Texas Instruments TMS320C28x Reference Manual page 296

LSLL ACC,T
SYNTAX OPTIONS
LSLL ACC,T
Operands ACC
T
T
Description
Flags and Z
Modes
N
Repeat
Example
; Logical shift left contents of VarA by VarB:
MOVL
MOV
LSLL
MOVL
0101 0110 0011 1011
Accumulator register
Upper 16 bits of the multiplicand (XT) register
Upper 16 bits of the multiplicand register (XT)
Perform a logical shift left on the content of the ACC register by the amount
specified by the five least significant bits of the T register, T(4:0) = 0...31.
Higher order bits are ignored. During the shift, the low order bits of the ACC
register are zero filled. If T specifies a shift of 0, then C is cleared; otherwise,
C is filled with the last bit to be shifted out of the ACC register:
Last bit out or cleared
C
Discard
other bits
After the shift, the Z flag is set if the ACC value is zero, else Z is cleared. Even
if the T register specifies a shift of 0, the content of the ACC register is still
tested for the zero condition and Z is affected.
After the shift, the N flag is set if bit 31 of the ACC is 1, else N is cleared. Even
if the T register specifies a shift of 0, the content of the ACC register is still
tested for the negative condition and N is affected.
This instruction is not repeatable. If this instruction follows the RPT
instruction, it resets the repeat counter (RPTC) and executes only once.
ACC,@VarA
T,@VarB
ACC,T
@VarA,ACC
Logical Shift Left by T (4:0)
OPCODE OBJMODE
ACC
Left shift
(Contents of T (4:0)
ACC
; ACC = VarA
; T = VarB (shift value)
; Logical shift left ACC by T(4:0)
; Store result into VarA
LSLL ACC,T
RPT CYC
1 − 1
0
6-139