Pipeline Protection - Texas Instruments TMS320C28x Reference Manual

Pipeline Protection

4.4 Pipeline Protection
4.4.1 Protection During Reads and Writes to the Same Data-Space Location
4-12
Instructions are being executed in parallel in the pipeline, and different instruc-
tions perform modifications to memory and registers during different phases
of completion. In an unprotected pipeline, this could lead to pipeline conflicts—
reads and writes at the same location happening out of the intended order.
However, the C28x pipeline has a mechanism that automatically protects
against pipeline conflicts. There are two types of pipeline conflicts that can
occur on the C28x:
Conflicts during reads and writes to the same data-space location
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Register conflicts
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The pipeline prevents these conflicts by adding inactive cycles between
instructions that would cause the conflicts. Sections 4.4.1 and 4.4.2 explain
the circumstances under which these pipeline-protection cycles are added
and tells how to avoid them, so that you can reduce the number of inactive
cycles in your programs.
Consider two instructions, A and B. Instruction A writes a value to a memory
location during its W phase. Instruction B must read that value from the same
location during its R1 and R2 phases. Because the instructions are being
executed in parallel, it is possible that the R1 phase of instruction B could occur
before the W phase of instruction A. Without pipeline protection, instruction B
could read too early and fetch the wrong value. The C28x pipeline prevents
that read by holding instruction B in its D2 phase until instruction A is finished
writing.
Example 4−4 shows a conflict between two instructions that are accessing the
same data-memory location. The pipeline activity shown is for an unprotected
pipeline. For convenience, the F1−D1 phases are not shown. I1 writes to VarA
during cycle 5. Data memory completes the store in cycle 6. I2 should not read
the data-memory location any sooner than cycle 7. However, I2 performs the
read during cycle 4 (three cycles too early). To prevent this kind of conflict, the
pipeline-protection mechanism would hold I2 in the D2 phase for 3 cycles.
During these pipeline-protection cycles, no new operations occur.