Texas Instruments TMS320C28x Reference Manual page 483

SFR ACC,T
SFR ACC,T
SYNTAX OPTIONS
SFR ACC,T
Operands ACC
T
Description
Flags and Z
Modes
N
C
SXM
Repeat
Example
; Arithmetic shift right contents of VarA by VarB:
MOVL
MOV
SETC
SFR
MOVL
6-326
1111 1111 0101 0001
Accumulator register
Upper 16-bits of the multiplicand (XT) register
Right shift the content of the ACC register by the amount specified in the four
least significant bits of the T register, T(3:0) = 0..15. Higher order bits are
ignored. The type of shift (arithmetic or logical) is determined by the state of
the sign extension mode (SXM) bit:
if(SXM = 1)
ACC = S:ACC >> T(3:0);
else
ACC = 0:ACC >> T(3:0);
After the shift, the Z flag is set if the ACC value is zero, else Z is cleared. Even
if the T register specifies a shift of 0, the content of the ACC register is still
tested for the zero condition and Z is affected.
After the shift, the N flag is set if bit 31 of the ACC is 1, else N is cleared. Even
if the T register specifies a shift of 0, the content of the ACC register is still
tested for the negative condition and N is affected.
If (T(3:0) = 0) then C is cleared; otherwise, the last bit shifted out is loaded
into the C flag bit.
if (SXM = 1), then the operation behaves like an arithmetic right shift.
If (SXM = 0), then the operation behaves like a logical right shift.
This instruction is repeatable. If the operation follows a RPT instruction, then
the SFR instruction will be executed N+1 times. The state of the Z, N and C
flags will reflect the final result.
ACC,@VarA
T,@VarB
SXM
ACC,T
@VarA,ACC
OPCODE OBJMODE
// sign extension mode enabled
// arithmetic shift right
// sign extension mode disabled
// logical shift right
; ACC = VarA
; T = VarB (shift value)
; Enable sign extension mode
; Arithmetic shift right ACC by T(3:0)
; Store result into VarA
Shift Accumulator Right
RPT CYC
X − 1