A−1. Status Register St0 - Texas Instruments TMS320C28x Reference Manual

Register Figures
Figure A−1. Status register ST0
15 14 13 12
0 0 0 0
OVC/OVCU
R/W
Negative flag
0 Negative condition false
1 Negative condition true
Overflow flag
0 Flag is reset
1 Overflow detected
Product shift mode
0 0 0 Left shift by 1
0 0 1 No shift
0 1 0 Right shift by 1, sign extended
0 1 1 Right shift by 2, sign extended
1 0 0 Right shift by 3, sign extended
1 0 1 Right shift by 4, sign extended
1 1 0 Right shift by 5, sign extended
1 1 1 Right shift by 6, sign extended
Overflow counter
Behaves differently for signed and unsigned
operations:
Signed operations (OVC)
Increments by 1 for each positive overflow;
Decrements by 1 for each negative overflow.
Unsigned operations (OVCU)
Increments by 1 for ADD operations that
generate a Carry
Decrements by 1 for SUB operations that
generate a Borrow
Note: For more details about ST0, see section 2.3 on page 2-16.
11 10 9 8 7
É É É
0 0 0 0 0
É É É
PM
É É É
R/W
6 5 4
0 0 0
V N Z
R/W R/W R/W
Sign-extension mode
0 Sign extension suppressed
1 Sign extension mode selected
ACC overflow mode
0 Results overflow normally
1 Overflow mode selected
Test/control flag
Holds result of test performed
by TBIT or NORM instruction
Carry bit
0 Carry not detected/borrow detected
1 Carry detected/borrow not detected
Zero flag
0 Zero condition false
1 Zero condition true
3 2 1 0
0 0 0 0
C TC OVM SXM
R/W R/W R/W
R/W