Real-Time Mode Execution States - Texas Instruments TMS320C28x Reference Manual

Execution Control Modes
Figure 7−3. Real-time Mode Execution States
Single-instruction state
Cannot observe CPU
Can service an interrupt
if RUN 1 used
After executing
one instruction
†
If you use a RUN 1 command to execute a single instruction, an interrupt can be serviced in the single-instruction state. If you use
a STEP 1 command for the same purpose, an interrupt cannot be serviced.
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used, the CPU can service the interrupt. If a STEP 1 command was used, the
CPU cannot, even if the interrupt is NMI or RS. In real-time mode, if the
DBGM bit is 1 (debug events are disabled), a RUN 1 or STEP 1 command
forces continuous execution of instructions until DBGM is cleared.
Note: If you single-step an instruction in real−time emulation mode and that
instruction sets DBGM, the CPU continues to execute instructions until DBGM
is cleared. If you want to single-step through a non-time-critical interrupt ser-
vice routine (ISR), you must initiate a CLRC DBGM instruction at the beginning
of the ISR. Once you clear DBGM, you can single-step or place breakpoints.
Run state. This state is entered when you use a run command from the
-
debugger interface. The CPU executes instructions until a debugger com-
mand or a debug event returns the CPU to the debug-halt state.
The CPU can service all interrupts in this state. When an interrupt occurs
simultaneously with a debug event, the debug event has priority; however,
if interrupt processing began before the debug event occurred, the debug
event cannot be processed until the interrupt service routine begins.
Figure 7−3 illustrates the relationship among the three states. Notice that the
C28x cannot pass directly between the single-instruction and run states. No-
tice also that the CPU can be observed in the debug-halt state and in the run
state. In the single-instruction state, the contents of CPU registers and
memory are not updated in the debugger display. In the debug-halt and run
states, register and memory values are updated unless DBGM = 1. Maskable
interrupts occurring in any state are latched in the interrupt flag register (IFR).
†
Debugger command
Debug-halt state
Can observe CPU
Can service time-critical interrupts
(including NMI and RS)
Debugger command
Run state
Can observe CPU
Can service interrupts
Debugger command,
breakpoint, or analysis stop