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Table E−2. C2xLP Instructions and C28x Equivalent Instructions (Continued)
C2xLP
Instruc-
Mnemonic
tion
CLRC
XF/OVM/SXM/TC/C
CLRC
CNF
CMPL
CMPR
0/1/2/3
DMOV
loc16
IDLE
IN
loc16,PA
INTR
K
LACC
loc16[,0]
LACC
loc16,1..15
LACC
loc16,16
LACC
#16bit,0..15
LACL
loc16
LACL
#8bit
LACT
loc16
LAR
ARn,loc16
LAR
ARn,#8bit
LAR
ARn,#16bit
LDP
loc16
LDP
#9bit
LPH
loc16
LST
#0/1,loc16
LT
loc16
LTA
loc16
†
True/False
Cycles
Size
Instruc-
tion
n+1
16
CLRC
n+1
16
n+1
16
NOT
n+1
16
CMPR
n+1
16
DMOV
1
16
IDLE
2(n+1)
32
IN
4
16
n+1
16
MOV
n+1
16
MOV
n+1
16
MOV
2
32
MOV
n+1
16
MOVU
1
16
MOVB
n+1
16
MOV
2(n+1)
16
MOVZ
2
16
MOVB
2
32
MOVL
2(n+1)
16
2
16
MOVZ
n+l
16
MOV
2(n+1)
16
n+l
16
MOV
n+l
16
MOVA
C2xLP Instruction Set Compatibility
Condition Tests on Flags
C28x
Mnemonic
XF/OVM/SXM/TC/C
Not applicable
ACC
0/1/2/3
loc16
loc16,*(PA)
Not applicable
ACC,loc16 [<< 0]
ACC,loc16 << 1..15
ACC,loc16 << 16
ACC,#16bit << 0..15
ACC,loc16
ACC,#8bit
ACC,loc16 << T
ARn,loc16
XARn,#8bit
XARn,#22bit
Not applicable
DP,#10bit >> 1
PH,loc16
See Table D−7
T,loc16
T,loc16
Cycles
Size
2,1
16
1
16
1
16
n+1
16
5
16
n+2
32
1
16
1
32
1
16
1
32
1
16
1
16
1
32
1
16
1
16
1
32
1
16
1
16
1
16
n+1
16
E-5
- Quick Links:
- 1.1 Introduction to the Cpu
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