Texas Instruments TMS320C28x Reference Manual page 301

LSRL ACC,T
LSRL ACC,T
SYNTAX OPTIONS
LSRL ACC,T
Operands ACC
T
Description
Flags and Z
Modes
N
C
Repeat
Example
; Logical shift right contents of VarA by VarB:
MOVL
MOV
LSRL
MOVL
6-144
0101 0110 0010 0010
Accumulator register
Upper 16 bits of the multiplicand (XT) register
Perform an logical shift right on the content of the ACC register as specified
by the five least significant bits of the T register, T(4:0) = 0...31. Higher order
bits are ignored. During the shift, the high order bits of ACC are zero-filled. If
T specifies a shift of 0, then C is cleared; otherwise, C is filled with the last bit
to be shifted out of the ACC register:
0
After the shift, the Z flag is set if the ACC value is zero, else Z is cleared. Even
if the T register specifies a shift of 0, the content of the ACC register is still
tested for the zero condition and Z is affected.
After the shift, the N flag is set if bit 31 of the ACC is 1, else N is cleared. Even
if the T register specifies a shift of 0, the content of the ACC register is still
tested for the negative condition and N is affected.
If (T(4:0) = 0) then C is cleared; otherwise, the last bit shifted out is loaded
into the C flag bit.
This instruction is not repeatable. If this instruction follows the RPT
instruction, it resets the repeat counter (RPTC) and executes only once.
ACC,@VarA
T,@VarB
ACC,T
@VarA,ACC
Logical Shift Right by T (4:0)
OPCODE
ACC
Right shift
Contents of T (4:0)
ACC
; ACC = VarA
; T = VarB (shift value)
; Logical shift right ACC by T(4:0)
; Store result into VarA
OBJMODE RPT CYC
1 − 1
Last bit out or cleared
C
Discard
other bits