2.4 Status Register St1; Bit Fields Of Status Register 1 (St1) - Texas Instruments TMS320C28x Reference Manual

Status Register ST1

2.4 Status Register ST1

Figure 2−11.Bit Fields of Status Register 1 (ST1)
15
ARP
R/W-000
7 6
IDLESTAT EALLOW
R−0 R/W−0
ARP Auxiliary register pointer. This 3-bit field points to the current auxiliary register. This is one
of the 32-bit auxiliary registers (XAR0−XAR7). The mapping of ARP values to auxiliary reg-
Bits 15−13
isters is as follows:
XF XF status bit. This bit reflects the current state of the XFS output signal, which is com-
patible to the C2XLP CPU. This bit is set by the "SETC XF" instruction. This bit is
Bit 12
cleared by the "CLRC XF" instruction. The pipeline is not flushed when setting or clear-
ing this bit using the given instructions. This bit can be saved and restored by interrupts
and when restoring the ST1 register. This bit is set to 0 on reset.
M0M1MAP M0 and M1 mapping mode bit. The M0M1MAP bit should always remain set to 1 in
the C28x object mode. This is the default value at reset. The M0M1MAP bit may be set
Bit 11
low when operating in C27x-compatible mode. The effect of this bit, when low, is to
swap the location of blocks M0 and M1 only in program space and to set the stack
pointer default reset value to 0x000. C28x mode users should never set this bit to 0.
2-34
The following figure shows the bit fields of status register ST1. All of these bit
fields are modified in the decode 2 phase of the pipeline. Detailed descriptions
of these bits follow the figure.
13 12
XF
R/W−0
5 4
LOOP SPA
R−0 R/W−0
ARP
000
001
010
100
101
11 10
Reserved
M0M1MAP
R/W−1 R/W−0
3 2
VMAP PAGE0
R/W−1 R/W−0
Selected Auxiliary Register
XAR0 (selected at reset)
XAR1
XAR2
011 XAR3
XAR4
XAR5
110 XAR6
111 XAR7
9 8
AMODE
OBJMODE
R/W−0 R/W−0
1 0
DBGM INTM
R/W−1 R/W−1