Texas Instruments TMS320C28x Reference Manual page 62

Status Register (ST0)
OVM Overflow mode bit. When ACC accepts the result of an addition or subtraction and the
result causes an overflow, OVM determines how the CPU handles the overflow as fol-
Bit 1
lows:.
This bit can be individually set and cleared by the SETC OVM instruction and
CLRC OVM instruction, respectively. At reset, OVM is cleared.
SXM Sign-extension mode bit. SXM affects the MOV, ADD, and SUB instructions that use a
16-bit value in an operation on the 32-bit accumulator. When the 16-bit value is loaded
Bit 0
into (MOV), added to (ADD), or subtracted from (SUB) the accumulator, SXM deter-
mines whether the value is sign extended during the operation as follows:
SXM also determines whether the accumulator is sign extended when it is shifted right
by the SFR instruction. SXM does not affect instructions that shift the product register
value; all right shifts of the product register value use sign extension.
This bit can be individually set and cleared by the SETC SXM instruction and
CLRC SXM instruction, respectively. At reset, SXM is cleared. Table 2−10 lists the in-
structions that are affected by SXM. See Chapter 6 for more details on instructions.
2-32
0 Results overflow normally in ACC. The OVC reflects the overflow (see the de-
scription for the OVC on page 2-16)
1 ACC is filled with either its most positive or most negative value as follows:
If ACC overflows in the positive direction (from 7FFF FFFF
ACC is then filled with 7FFF FFFF
If ACC overflows in the negative direction (from 8000 0000
ACC is then filled with 8000 0000
0 Sign extension is suppressed. (The value is treated as unsigned.)i
1 Sign extension is enabled. (The value is treated as signed.)
.
16
.
16
to 8000 0000 ),
16 16
to 7FFF FFFF ),
16 16