Texas Instruments TMS320C28x Reference Manual page 515

SUBUL P,loc32
SUBUL P,loc32
SYNTAX OPTIONS
SUBUL P,loc32
Operands P
loc32
Description
Flags and Z
Modes
N
C
V
OVCU
Repeat
Example
; Subtract 64-bit VarA − VarB and store result in VarC:
MOVL
MOVL
SUBUL P,@VarB+0
SUBBL ACC,@VarB+2
MOVL
MOVL
6-358
Product register
Addressing mode (see Chapter 5)
Subtract from the P register the 32-bit content of the location pointed to by
the "loc32" addressing mode. The addition is treated as an unsigned SUB
operation:
P = P − [loc32];
Note: The difference between a signed and unsigned 32-bit subtract is in the treatment of the
overflow counter (OVC). For a signed SUBL, the OVC counter monitors
positive/negative overflow. For an unsigned SUBL, the OVC unsigned (OVCU) counter
monitors the borrow.
After the subtraction, the Z flag is set if the P value is zero, else Z is cleared.
After the subtraction, the N flag is set if bit 31 of P is 1, else N is cleared.
If the subtraction generates a borrow, C is cleared; otherwise C is set.
If a signed overflow occurs, V is set; otherwise V is not affected.
The overflow counter is decremented whenever a subtraction operation
generates an unsigned borrow. The OVM mode does not affect the OVCU
counter.
This instruction is not repeatable. If this instruction follows the RPT
instruction, it resets the repeat counter (RPTC) and executes only once.
P,@VarA+0 ; Load P with low 32-bits of VarA
ACC,@VarA+2 ; Load ACC with high 32-bits of VarA
; Sub from P unsigned low 32-bits of VarB
; Sub from ACC with borrow high 32-bits of VarB
@VarC+0,P ; Store low 32-bit result into VarC
@VarC+2,ACC ; Store high 32-bit result into VarC
Subtract Unsigned 32-bit Value
OPCODE
0101 0110 0101 1101
0000 0000 LLLL LLLL
// unsigned subtract
OBJMODE RPT CYC
1 − 1