Texas Instruments TMS320C28x Reference Manual page 669

Glossary
indirect addressing modes: Addressing modes that use pointers to ac-
cess memory. The available pointers are auxiliary registers AR0−AR5,
extended auxiliary registers XAR6 and XAR7, and the stack pointer (SP).
instruction boundary: The point where the CPU has finished one instruc-
tion and is considering what it will do next — move on to the next instruc-
tion.
instruction counter (IC): The register that points to the instruction in the de-
code 1 phase (the instruction that is to enter the decode 2 phase next).
Also, on an interrupt or call operation, the IC value represents the return
address, which is saved to the stack or to auxiliary register XAR7.
instruction-fetch mechanism: The hardware for the fetch 1 and fetch 2
phases of the pipeline. This hardware is responsible for fetching instruc-
tions from program memory and filling an instruction-fetch queue.
instruction-fetch queue: A queue of four 32-bit registers that receives
fetched instructions and holds them for decoding. When a program-flow
discontinuity occurs, the instruction-fetch queue is emptied.
instruction-not-available condition: The condition that occurs when the
decode 2 pipeline hardware requests an instruction but there are no in-
structions waiting in the instruction-fetch queue. This condition causes
the decode 2 through write phases of the pipeline to freeze until one or
more new instructions have been fetched.
instruction register: The register that contains the instruction that has
reached the decode 2 pipeline phase.
instruction word: Either an entire 16-bit opcode or one of the halves of a
32-bit opcode.
INT1−INT14: Fourteen general-purpose interrupts that are triggered by sig-
nals at pins of the same names. These interrupts are maskable and have
corresponding bits in the interrupt flag register (IFR), the interrupt enable
register (IER), and the debug interrupt enable register (DBGIER).
Interrupt boundary: An instruction boundary where the CPU can insert an
interrupt between two instructions. See also instruction boundary.
interrupt enable bits: Bits responsible for enabling or disabling maskable
interrupts. The enable bits are all the bits in the interrupt enable register
(IER), all the bits in the debug interrupt enable register (DBGIER), and
the interrupt global mask bit (INTM in status register ST1).
interrupt enable register (IER): Each of the maskable interrupts has an in-
terrupt enable bit in this register. If a bit in the IER is 1, the corresponding
interrupt is enabled; otherwise, it is disabled. See also debug interrupt
enable register (DBGIER).