Texas Instruments TMS320C28x Reference Manual page 105

Table 3−5. Registers After Reset (Continued)
Register Bit(s)
ST1 ‡ 0: INTM
1: DBGM
2: PAGE0
3: VMAP
4: SPA
5: LOOP
6: EALLOW
7: IDLESTAT
8: AMODE
9: OBJMODE
10: Reserved
11: M0M1MAP 1
Note: The registers listed in this table are introduced in section 2.2, CPU Registers, on page
2-4.
Value After Reset
1
1
0
1
0
0
0
0
0
0
0
CPU Interrupts and Reset
Hardware Reset (RS)
Comments
Maskable interrupts are
globally disabled. They
cannot be serviced unless
the C28x is in real-time
mode with the CPU
halted.
Emulation accesses and
events are disabled.
PAGE0 stack addressing
mode is enabled. PAGE0
direct addressing mode is
disabled.
The interrupt vectors are
mapped to program-
memory addresses
3F FFC0 −3F FFFF .
16 16
Access to emulation regis-
ters is disabled.
C27x/C28x addressing
mode
C27x object mode
3-25