Instructions Affected By V Flag - Texas Instruments TMS320C28x Reference Manual

V Overflow flag. If the result of an operation causes an overflow in the register holding the
result, V is set and latched. If no overflow occurs, V is not modified. Once V is latched, it
Bit 6
remains set until it is cleared by reset or by a conditional branch instruction that tests V.
Such a conditional branch clears V regardless of whether the tested condition (V = 0 or
V = 1) is true.
An overflow occurs in ACC (and V is set) if the result of an addition or subtraction does not
fit within the signed numerical range −2
An overflow occurs in AH, AL, or another 16-bit register or data-memory location if the result
of an addition or subtraction does not fit within the signed numerical range −2
1), or 8000
The instructions CMP, CMPB and CMPL do not affect the state of the V flag. Table 2−6 lists
the instructions that are affected by V flag. See Chapter 6 for more details on instructions.
V can be summarized as follows:
0
1
to 7FFF .
16 16
V has been cleared.
An overflow has been detected, or V has been set.
Table 2−6. Instructions Affected by V flag
Instruction
ABS ACC
ABSTC ACC
ADD ACC,#16bit << shift
ADD ACC,loc16 << shift
ADD ACC,loc16 << T
ADD AX,loc16
ADD loc16,#16bitSigned
ADD loc16,AX
ADDB ACC,#8bit
ADDB AX,#8bitSigned
ADDCL ACC,loc32
ADDCU ACC,loc16
ADDL ACC,loc32
ADDL loc32,ACC
ADDU ACC,loc16
ADDUL ACC,loc32
31 31
to (+2 − 1), or 8000 0000
Description
if(ACC == 0x8000 0000) V = 1
if(ACC == 0x8000 0000) V = 1
V = 1 on signed overflow
V = 1 on signed overflow
V = 1 on signed overflow
V = 1 on signed overflow
V = 1 on signed overflow
V = 1 on signed overflow
V = 1 on signed overflow
V = 1 on signed overflow
V = 1 on signed overflow
V = 1 on signed overflow
V = 1 on signed overflow
V = 1 on signed overflow
V = 1 on signed overflow
V = 1 on signed overflow
Central Processing Unit
Status Register (ST0)
to 7FFF FFFF .
16 16
15 15
to (+2 −
2-21