Texas Instruments TMS320C28x Reference Manual page 227

Dsp cpu and instruction set
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CLRC OVC
CLRC OVC
SYNTAX OPTIONS
CLRC OVC
Note:
This instruction is an alias for the "ZAP OVC" operation.
Operands
OVC
Description
Flags and
OVC
Modes
Repeat
Example
; Calculate: VarD = sat(VarA + VarB + VarC)
CLRC OVC
MOVL ACC,@VarA
ADDL ACC,@VarB
ADDL ACC,@VarC
SAT
MOVL @VarD,ACC
6-70
Overflow counter bits in Status Register 0 (ST0)
Clear the overflow counter (OVC) bits in ST0.
The 6-bit overflow counter bits (OVC) are cleared.
This instruction is not repeatable. If this instruction follows the RPT
instruction, it resets the repeat counter (RPTC) and executes only once.
ACC
OPCODE
0101 0110 0101 1100
; Zero overflow counter
; ACC = VarA
; ACC = ACC + VarB
; ACC = ACC + VarC
; Saturate if OVC != 0
; Store saturated result into VarD
Clear Overflow Counter
OBJMODE
RPT
CYC
1
1

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