Texas Instruments TMS320C28x Reference Manual page 173

Register Operations
Table 6−2. Register Operations (Continued)
Mnemonic
Status Register Operations (ST0, ST1) (Continued)
CLRC OVC
ZAP OVC
DINT
EINT
MOV PM,AX
MOV OVC,loc16
MOVU OVC,loc16
MOV loc16,OVC
MOVU loc16,OVC
SETC Mode
SETC XF
SETC M0M1MAP
C28MAP
SETC OBJMODE
C28OBJ
SETC AMODE
LPADDR
SPM PM
Miscellaneous Operations
ABORTI
ASP
EALLOW
IDLE
NASP
NOP {*ind}
ZAPA
EDIS
6-16
Description
Clear OVC bits
Clear overflow counter
Disable maskable interrupts (set INTM bit)
Enable maskable interrupt (clear INTM bit)
Load product shift mode bits PM = AX(2:0)
Load the overflow counter
Load overflow counter with unsigned value
Store the overflow counter
Store the unsigned overflow counter
Set multiple status bits
Set XF bit and output signal
Set M0M1MAP bit
Set the M0M1MAP bit
Set OBJMODE bit
Set the OBJMODE bit
Set AMODE bit
Alias for SETC AMODE
Set product shift mode bits
Abort interrupt
Align stack pointer
Enable access to protected space
Put processor in IDLE mode
Un-align stack pointer
No operation with optional indirect address modification
Zero accumulator P register and OVC
Disable access to protected space
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