Texas Instruments TMS320C28x Reference Manual page 674

P
overflow counter (OVC): A 6-bit counter in status register ST0 that can be
used to track overflows in the accumulator (ACC). The OVC is enabled
only when the overflow mode (OVM) bit in ST0 is 0. When OVM = 0, the
OVC is incremented by 1 for every overflow in the positive direction (too
large a positive number) and decremented by 1 for every overflow in the
negative direction (too large a negative number). The saturate (SAT) in-
struction modifies ACC to reflect the net overflow represented in the
OVC.
overflow flag (V): A bit in status register ST0 that indicates when the result
of an operation causes an overflow in the location holding the result
(V = 1). If no overflow occurs, V is not modified.
overflow mode (OVM) bit: A bit in the status register ST0 that enables or
disables overflow mode. When overflow mode is on (OVM = 1) and an
overflow occurs, the CPU fills the accumulator (ACC) with a saturation
value. When overflow mode is off (OVM = 0), the CPU lets ACC overflow
normally but keeps track of each overflow by incrementing or decrement-
ing by 1 the overflow counter (OVC) in ST0.
P register: See product register (P).
PAB: See program address bus (PAB).
PAGE0 bit: PAGE0 addressing mode configuration bit. This bit, in status
register ST1, selects between two addressing modes: PAGE0 stack ad-
dressing mode (PAGE = 0) and PAGE0 direct addressing mode
(PAGE0 = 1).
PAGE0 direct addressing mode: The direct addressing mode that uses
data page 0 regardless of the value in the data page pointer (DP). This
mode is available only when the PAGE0 bit in status register ST1 is 1.
See also DP direct addressing mode and PAGE0 stack addressing
mode.
PAGE0 stack addressing mode: The indirect addressing mode that refer-
ences a value on the stack by subtracting a 6-bit offset from the current
position of the stack pointer (SP). This mode is available only when the
PAGE0 bit in status register ST1 is 0. See also stack-pointer indirect ad-
dressing mode.
PC: See program counter (PC).
pending interrupt: An interrupt that has been requested but is waiting for
approval from the CPU. See also approve an interrupt request.
Glossary
Glossary G-15