Texas Instruments TMS320C28x Reference Manual page 408

NORM ACC, *ind
SYNTAX OPTIONS
NORM ACC, *
NORM ACC, *++
NORM ACC, *− −
NORM ACC, *0++
NORM ACC, *0− −
Operands ACC
*ind
Description
Flags and Z
Modes Modes
N
TC
ARP
Repeat
Normalize ACC and Modify Selected Auxiliary Register
0101 0110 0010 0100
0101 0110 0101 1010
0101 0110 0010 0000
0101 0110 0111 0111
0101 0110 0011 0000
Accumulator register
*, *++, *−−, *0++, *0−− indirect addressing modes (see Chapter 5)
Normalize the signed content of the ACC register and modify, as specified by
the indirect addressing mode, the auxiliary register (XAR0 to XAR7) pointed
to by the auxiliary register pointer (ARP):
Note: The NORM instruction normalizes a signed number in the ACC register by finding the
magnitude of the number. An XOR operation is performed on ACC bits 31 and 30. If the
bits are the same, then the content of the ACC register is logically shifted left by 1 to
eliminate the extra sign bit and the selected pointer is modified. If the bits are different,
the ACC is not shifted and the selected pointer is not modified. The selected pointer
does not access any memory location.
After the operation, the Z flag is set if the ACC value is zero, else Z is cleared.
After the operation, the N flag is set if bit 31 of the ACC is 1, else N is cleared.
If the operation set TC, no normalization was needed (ACC did not need to
be modified). If the operation cleared TC, bits 31 and 30 were the same and,
as a result, the ACC register was logically shifted left by 1.
Auxiliary register pointer selects which pointer to modify as part of the
operation (XAR0 to XAR7).
This instruction is repeatable. If the operation follows a RPT instruction, then
the NORM instruction will be executed N+1 times. The state of the Z, N, and
TC flags will reflect the final result. Note: If you only want the NORM
instruction to execute until normalization is done, you can create a loop that
checks the value of the TC bit. When TC = 1, normalization is complete.
OPCODE OBJMODE
NORM ACC, *ind
RPT CYC
1 Y N+4
1 Y N+4
1 Y N+4
1 Y N+4
1 Y N+4
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