Texas Instruments TMS320C28x Reference Manual page 680

T
U
T register: The primary function of this register, also called the multiplicand
register, is to hold one of the values to be multiplied during a multiplica-
tion. The following shift instructions use the four LSBs to hold the shift
count: ASR (arithmetic shift right), LSL (logical shift left), LSR (logical
shift right), and SFR (shift accumulator right). The T register can also be
used as a general-purpose 16-bit register.
TAP: See test access port (TAP).
target device/system: The device/system on which the code you have de-
veloped is executed.
TC bit: See test/control flag (TC).
test access port (TAP): A standard communication port defined by IEEE
standard 1149.1−1990 included in the DSP to implement boundary scan
functions and/or to provide communication between the DSP and emula-
tor.
test/control flag (TC): A bit in status register ST0 that shows the result of
a test performed by the TBIT (test bit) instruction or the NORM (normal-
ize) instruction.
test-logic-reset: A test and emulation logic condition that occurs when the
TRST signal is pulled low or when the TMS signal is used to advance the
JTAG state machine to the TLR state. This logic is a different type than
that used by the CPU, which resets functional logic.
32-bit operation: An operation that reads or writes 32 bits.
TI extension pins: See EMU0 and EMU1 pins.
time-critical interrupt: An interrupt that must be serviced even when back-
ground code is halted. For example, a time-critical interrupt might service
a motor controller or a high-speed timer. See also debug interrupt enable
register (DBGIER).
USER1−USER12 interrupts: The interrupt vector table contains twelve
locations for user-defined software interrupts. These interrupts, called
USER1−USER12 in this document, can be initiated only by way of the
TRAP instruction.
Glossary
Glossary G-21