Auxiliary Registers (Xar0−Xar7, Ar0−Ar7); Address Reach Of The Stack Pointer - Texas Instruments TMS320C28x Reference Manual

CPU Registers
Figure 2−7. Address Reach of the Stack Pointer
2.2.6 Auxiliary Registers (XAR0−XAR7, AR0−AR7)
2-12
Range accessible
by way of SP
Range not accessible
by way of SP
The operation of the stack is as follows:
The stack grows from low memory to high memory.
-
The SP always points to the next empty location in the stack.
-
At reset, the SP is initialized, so that it points to address 0000 0400
-
When 32-bit values are saved to the stack, the least significant 16 bits are
-
saved first, and the most significant 16 bits are saved to the next higher
address (little endian format).
When 32-bit operations read or write a 32-bit value, the C28x CPU expects
-
the memory wrapper or peripheral-interface logic to align that read or write
to an even address. For example, if the SP contains the odd address
0000 0083 , a 32-bit read operation reads from addresses 0000 0082
16
and 0000 0083 .
16
The SP overflows if its value is increased beyond FFFF
-
below 0000 . When the SP increases past FFFF
16
from 0000 . For example, if SP = FFFE
16
SP, the result is 0001
backward from FFFF
subtracts 4 from SP, the result is FFFE
When values are being saved to the stack, the SP is not forced to align with
-
even or odd addresses. Alignment is forced by the memory wrapper or pe-
ripheral-interface logic.
The CPU provides eight 32-bit registers that can be used as pointers to
memory or as general-purpose registers (see Section 5.6, Indirect Addressing
Data memory
0000 0000−0000 FFFF
0001 0000−FFFF FFFF
and an instruction adds 3 to the
16
. When the SP decreases past 0000
16
. For example, if SP = 0002
16
.
16
.
16
16
or decreased
16
, it counts forward
16
, it counts
16
and an instruction
16