Texas Instruments TMS320C28x Reference Manual page 671

Glossary
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JTAG: Joint Test Action Group. The Joint Test Action Group was formed in
1985 to develop economical test methodologies for systems designed
around complex integrated circuits and assembled with surface-mount
technologies. The group drafted a standard that was subsequently
adopted by IEEE as IEEE Standard 1149.1-1990, "IEEE Standard Test
Access Port and Boundary-Scan Architecture". See also boundary scan;
test access port (TAP).
JTAG port: See test access port (TAP).
latch: Hold a bit at the same value until a given event occurs. For example,
when an overflow occurs in the accumulator, the V bit is set and latched
at 1 until it is cleared by a conditional branch instruction or by a write to
status register ST0. An interrupt is latched when its flag bit has been
latched in the interrupt flag register (IFR).
least significant bit (LSB): The bit in the lowest position of a binary number.
For example, the LSB of a 16-bit register value is bit 0. See also MSB,
LSByte, and MSByte.
least significant byte (LSByte): The byte in the lowest position of a binary
value. The LSByte of a value consists of the eight LSBs. See also
MSByte, LSB, and MSB.
location: A space where data can reside. A location may be a CPU register
or a space in memory.
logical shift: A shift that treats the shifted value as unsigned. See also arith-
metic shift.
LOOP (loop instruction status) bit: A bit in status register ST1 that indi-
cates when a LOOPNZ or LOOPZ instruction is being executed
(LOOP = 1).
low addresses: Addresses closer to 00 0000
also high addresses.
low bits: See LSB.
low word: The 16 LSBs of a 32-bit value. See also high word.
than to 3F FFFF . See
16 16