Texas Instruments TMS320C6712D User Manual
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Texas Instruments TMS320C6712D User Manual

Texas Instruments TMS320C6712D User Manual

Floating point digital signal processor
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D
Low-Price/High-Performance Floating-Point
Digital Signal Processor (DSP):
TMS320C6712D
− Eight 32-Bit Instructions/Cycle
− 150-MHz Clock Rate
− 6.7-ns Instruction Cycle Time
− 900 MFLOPS
D
Advanced Very Long Instruction Word
(VLIW) C67x DSP Core
− Eight Highly Independent Functional
Units:
− Four ALUs (Floating- and Fixed-Point)
− Two ALUs (Fixed-Point)
− Two Multipliers (Floating- and
Fixed-Point)
− Load-Store Architecture With 32 32-Bit
General-Purpose Registers
− Instruction Packing Reduces Code Size
− All Instructions Conditional
D
Instruction Set Features
− Hardware Support for IEEE
Single-Precision and Double-Precision
Instructions
− Byte-Addressable (8-, 16-, 32-Bit Data)
− 8-Bit Overflow Protection
− Saturation
− Bit-Field Extract, Set, Clear
− Bit-Counting
− Normalization
D
L1/L2 Memory Architecture
− 32K-Bit (4K-Byte) L1P Program Cache
(Direct Mapped)
− 32K-Bit (4K-Byte) L1D Data Cache
(2-Way Set-Associative)
− 512K-Bit (64K-Byte) L2 Unified Mapped
RAM/Cache
(Flexible Data/Program Allocation)
D
Device Configuration
− Boot Mode: 8- and 16-Bit ROM Boot
− Little Endian, Big Endian
D
Enhanced Direct-Memory-Access (EDMA)
Controller (16 Independent Channels)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TMS320C67x and C67x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
Other trademarks are the property of their respective owners.
† IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
‡ These values are compatible with existing 1.26V designs.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
FLOATING POINT DIGITAL SIGNAL PROCESSOR
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POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005
16-Bit External Memory Interface (EMIF)
− Glueless Interface to Asynchronous
Memories: SRAM and EPROM
− Glueless Interface to Synchronous
Memories: SDRAM and SBSRAM
− 256M-Byte Total Addressable External
Memory Space
Two Multichannel Buffered Serial Ports
(McBSPs)
− Direct Interface to T1/E1, MVIP, SCSA
Framers
− ST-Bus-Switching Compatible
− Up to 256 Channels Each
− AC97-Compatible
− Serial-Peripheral-Interface (SPI)
Compatible (Motorola)
Two 32-Bit General-Purpose Timers
Flexible Software-Configurable PLL-Based
Clock Generator Module
A Dedicated General-Purpose Input/Output
(GPIO) Module With 5 Pins
†
IEEE-1149.1 (JTAG
)
Boundary-Scan-Compatible
272-Pin Ball Grid Array (BGA) Package
(GDP and ZDP Suffix)
CMOS Technology
− 0.13-µm/6-Level Copper Metal Process
‡
3.3-V I/Os, 1.20
-V Internal
Copyright  2005, Texas Instruments Incorporated
TMS320C6712D
1

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Summary of Contents for Texas Instruments TMS320C6712D

  • Page 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TMS320C67x and C67x are trademarks of Texas Instruments.

  • Page 2: Table Of Contents

    TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 revision history ........

  • Page 3: Revision History

    The TMS320C6712D device-specific documentation has been split from TMS320C6712, TMS320C6712C, TMS320C6712D Floating−Point Digital Signal Processors, literature number SPRS148L, into a separate Data Sheet, literature number SPRS293. It also highlights technical changes made to SPRS293 to generate SPRS293A; these changes are marked by “[Revision A]” in the Revision History table below Scope: Updated information on McBSP and JTAG for clarification.
  • Page 4 TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 PAGE(S) RESET TIMING section: Added Note MULTICHANNEL BUFFERED SERIAL PORT TIMING: switching characteristics over recommended operating conditions for McBSP section: Updated McBSP Timings figure for clarification ADDITIONS/CHANGES/DELETIONS •...

  • Page 5: Gdp And Zdp Bga Package (Bottom View)

    TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 GDP and ZDP BGA package (bottom view) GDP and ZDP 272-PIN BALL GRID ARRAY (BGA) PACKAGE ( BOTTOM VIEW ) • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443...

  • Page 6: Description

    TMS320C6000 and C6000 are trademarks of Texas Instruments. Windows is a registered trademark of the Microsoft Corporation. † Throughout the remainder of this document, the TMS320C6712D shall be referred to as its individual full device part number or abbreviated as C6712D or 12D.

  • Page 7: Device Characteristics

    † This value is compatible with existing 1.26V designs. ‡ PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

  • Page 8: Device Compatibility

    For a more detailed discussion on the migration of a C6712 device to a TMS320C6712C device, see the Migrating from TMS320C6712 to TMS320C6712C application report (literature number SPRA852). TMS320C62x and C67x are trademarks of Texas Instruments. † This value is compatible with existing 1.26V designs.

  • Page 9: Functional Block And Cpu (Dsp Core) Diagram

    A Register File .L1 † .S1 † .M1 † .D1 Power-Down Logic PLL ‡ • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6712D Digital Signal Processor L1P Cache Direct Mapped 4K Bytes Total C67x CPU (DSP Core) Instruction Fetch Control...

  • Page 10: Cpu (Dsp Core) Description

    While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store instructions are byte-, half-word, or word-addressable. C62x is a trademark of Texas Instruments. • POST OFFICE BOX 1443...
  • Page 11 Á Á Á Á Á Á • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6712D Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á...

  • Page 12: Memory Map Summary

    TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 memory map summary Table 2 shows the memory map address ranges of the device. Internal memory is always located at address 0 and can be used as both program and data memory. The configuration registers for the common peripherals are located at the same hex address ranges.

  • Page 13: Peripheral Register Descriptions

    Controls CE3 range B000 0000 − B0FF FFFF Controls CE3 range B100 0000 − B1FF FFFF Controls CE3 range B200 0000 − B2FF FFFF Controls CE3 range B300 0000 − B3FF FFFF Reserved • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6712D...
  • Page 14 TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 peripheral register descriptions (continued) HEX ADDRESS RANGE ACRONYM 019C 0000 MUXH 019C 0004 MUXL 019C 0008 EXTPOL 019C 000C − 019F FFFF − HEX ADDRESS RANGE...
  • Page 15 QDMA destination address register QDMA index register Reserved QDMA pseudo options register QDMA pseudo source address register QDMA pseudo frame count register QDMA pseudo destination address register QDMA pseudo index register • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6712D EDMA Parameter †...
  • Page 16 TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 peripheral register descriptions (continued) HEX ADDRESS RANGE ACRONYM 01B7 C000 PLLPID 01B7 C004 − 01B7 C0FF − 01B7 C100 PLLCSR 01B7 C104 − 01B7 C10F −...
  • Page 17 PCRx McBSPx pin control register − Reserved • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6712D COMMENTS COMMENTS Determines the operating mode of the timer, monitors the timer status, and controls the function of the TOUT pin. Contains the number of timer input clock cycles to count.

  • Page 18: Signal Groups Description

    TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 signal groups description CLKIN CLKOUT3 CLKOUT2 † CLKMODE0 PLLHV TRST EMU0 EMU1 EMU2 EMU3 EMU4 EMU5 ED[15:0] EA[21:2] † The CLKOUT2 pin is multiplexed with the GP[2] pin. Default function is CLKOUT2. To use this pin as GPIO, the GP2EN bit in the GPEN register and the GP2DIR bit in the GPDIR register must be properly configured.
  • Page 19 Transmit Receive Receive Clock Clock McBSPs (Multichannel Buffered Serial Ports) GPIO General-Purpose Input/Output (GPIO) Port Figure 4. Peripheral Signals • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6712D TOUT0 TINP0 CLKX0 FSX0 CLKR0 FSR0 CLKS0 GP[7](EXT_INT7) GP[6](EXT_INT6) GP[5](EXT_INT5) GP[4](EXT_INT4) CLKOUT2/GP[2]...

  • Page 20: Device Configurations

    TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 On the device, bootmode and certain device configurations/peripheral selections are determined at device reset. Other device configurations (e.g., EMIF input clock source) are software-configurable via the device configurations register (DEVCFG) [address location 0x019C0200] after device reset.
  • Page 21 01 – CE1 width 8-bit, Asynchronous external ROM boot with default timings (default mode) 10 − CE1 width 16-bit, Asynchronous external ROM boot with default timings 11 − Reserved, do not use 0 – Reserved. Do not use. 1 − CLKIN square wave [default] • HOUSTON, TEXAS 77251−1443 TMS320C6712D...
  • Page 22 TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 DEVICE CONFIGURATIONS (CONTINUED) DEVCFG register description The device configuration register (DEVCFG) allows the user control of the EMIF input clock source. For more detailed information on the DEVCFG register control bits, see Table 15 and Table 16.

  • Page 23: Terminal Functions

    TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 TERMINAL FUNCTIONS The terminal functions table identifies the external signal names, the associated pin (ball) numbers along with the mechanical package designator, the pin type (I, O/Z, or I/O/Z), whether the pin has any internal pullup/pulldown resistors and a functional pin description.
  • Page 24 TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 SIGNAL SIGNAL IPD/ IPD/ TYPE † TYPE † IPU ‡ ‡ NAME GDP/ CLKIN CLKOUT2 CLKOUT3 CLKMODE0 PLLHV TRST § EMU5 I/O/Z EMU4 I/O/Z EMU3 I/O/Z...
  • Page 25 EMIFBE pin must be externally pulled low. For more detailed information on the Big Endian mode correctness, see the EMIF Big Endian Mode Correctness portion of this data sheet. • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6712D...
  • Page 26 TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 SIGNAL SIGNAL IPD/ IPD/ TYPE † TYPE † IPU ‡ ‡ NAME GDP/ RESET −− EXT_INT7 EXT_INT6 EXT_INT5 EXT_INT4 EMIF − CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY #...
  • Page 27 TMS320C6000 DSP External Memory Interface (EMIF) Reference Guide (literature num- the TMS320C6000 DSP External Memory Interface (EMIF) Reference Guide (literature num- ber SPRU266)]. ber SPRU266)]. EMIF − DATA # External data External data • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6712D...
  • Page 28 TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 SIGNAL SIGNAL IPD/ IPD/ TYPE † TYPE † IPU ‡ NAME GDP/ I/O/Z I/O/Z I/O/Z I/O/Z TOUT1 TINP1 TOUT0 TINP0 MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)
  • Page 29 RESERVED FOR TEST − Reserved (leave unconnected, do not connect to power or ground) For proper device operation, the D12 pin must be externally pulled down with a 10-kΩ re- − sistor. • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6712D...
  • Page 30 TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 SIGNAL SIGNAL IPD/ IPD/ TYPE † TYPE † NAME GDP/ † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (PLL Filter)
  • Page 31 SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 Terminal Functions (Continued) DESCRIPTION DESCRIPTION ADDITIONAL RESERVED FOR TEST Reserved (leave unconnected, do not connect to power or ground) Reserved (leave unconnected, do not connect to power or ground) • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6712D...
  • Page 32 TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 SIGNAL SIGNAL TYPE † TYPE † NAME GDP/ 3.3-V supply voltage 3.3-V supply voltage DV DD DV DD (see the power-supply decoupling portion of this data sheet) (see the power-supply decoupling portion of this data sheet) 1.20-V supply voltage [See Note]...

  • Page 33: Ground Pins

    † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (PLL Filter) FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 Terminal Functions (Continued) DESCRIPTION DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED) GROUND PINS • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6712D...
  • Page 34 TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 SIGNAL SIGNAL TYPE † TYPE † NAME GDP/ Ground pins || Ground pins || The center thermal balls (J9−J12, K9−K12, L9−L12, M9−M12) [shaded] are all tied to ground and act as The center thermal balls (J9−J12, K9−K12, L9−L12, M9−M12) [shaded] are all tied to ground and act as...
  • Page 35 † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (PLL Filter) FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 Terminal Functions (Continued) DESCRIPTION GROUND PINS (CONTINUED) • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6712D...

  • Page 36: Development Support

    Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). For information on pricing and availability, contact the nearest TI field sales office or authorized distributor. Code Composer Studio, DSP/BIOS, and XDS are trademarks of Texas Instruments. •...

  • Page 37: Device Support

    The ZDP package, like the GDP package, is a 272-ball plastic BGA only with Pb-free balls. For device part numbers and further ordering information for TMS320C6712D in the GDP and ZDP package types, see the TI website (http://www.ti.com) or contact your TI sales representative.
  • Page 38 § For actual device part numbers (P/Ns) and ordering information, see the Mechanical Data section of this document or the TI website (www.ti.com). Figure 5. TMS320C6000 DSP Platform Device Nomenclature (Including the TMS320C6712D Device) MicroStar BGA and PowerPAD are trademarks of Texas Instruments.
  • Page 39 The Migrating from TMS320C6211(B)/6711(B) to TMS320C6711C application report (literature number SPRA837) describes the differences and issues of interest related to migration from the Texas Instruments TMS320C6211, TMS320C6211B, TMS320C6711, and TMS320C6711B devices, GFN packages, to the TMS320C6711C device, GDP package.

  • Page 40: Cpu Csr Register Description

    TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 CPU CSR register description The CPU control status register (CSR) contains the CPU ID and CPU Revision ID (bits 16−31) as well as the status of the device power-down modes [PWRD field (bits 15−10)], program and data cache control modes, the endian bit (EN, bit 8) and the global interrupt enable (GIE, bit 0) and previous GIE (PGIE, bit 1).
  • Page 41 = PD1, wake-up by an enabled or not enabled interrupt = PD2, wake-up by a device reset = PD3, wake-up by a device reset = Reserved Cache Enabled / Cache accessed and updated on reads. Cache Enabled / 2-Way Cache • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6712D...

  • Page 42: Cache Configuration (Ccfg) Register Description

    EDMA will assume a higher priority than the L1D memory system when accessing L2 memory. For more detailed information on the P-bit function and for silicon advisories concerning EDMA L2 memory accesses blocked, see the TMS320C6712, TMS320C6712C, TMS320C6712D Digital Signal Processors Silicon Errata (literature number SPRZ182C or later).

  • Page 43: Interrupt Sources And Interrupt Selector

    01100 00000 DSPINT 01101 00001 TINT0 01110 00010 TINT1 01111 10000 • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6712D Table 20. Interrupt Selector INTERRUPT MODULE EVENT − − TINT0 Timer 0 TINT1 Timer 1 SDINT EMIF GPINT4 † GPIO GPINT5 †...

  • Page 44: Edma Module And Edma Selector

    TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 EDMA module and EDMA selector The C67x EDMA for this device also supports up to 16 EDMA channels. Four of the sixteen channels (channels 8−11) are reserved for EDMA chaining, leaving 12 EDMA channels available to service peripheral devices. On this device, the user, through the EDMA selector registers, can control the EDMA channels servicing peripheral devices.
  • Page 45 R−0 Reserved R−0 24 23 22 21 Reserved R−0 Reserved R−0 DESCRIPTION • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6712D 20 19 EVTSEL2 R/W−00 0010b EVTSEL0 R/W−00 0000b 20 19 EVTSEL6 R/W−00 0110b EVTSEL4 R/W−00 0100b 20 19 EVTSEL14 R/W−00 1110b...

  • Page 46: Pll And Pll Controller

    SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 PLL and PLL controller The TMS320C6712D includes a PLL and a flexible PLL controller peripheral consisting of a prescaler (D0) and four dividers (OSCDIV1, D1, D2, and D3). The PLL controller is able to generate different clocks for different parts of the system (i.e., DSP core, Peripheral Data Bus, External Memory Interface, McASP, and other...
  • Page 47 CK2EN = 1 (EMIF GBLCTL.[3]) OD1EN = 1 (OSCDIV1.[15]) EKSRC = 0 (DEVCFG.[4]) EKEN = 1 (EMIF GBLCTL.[5]) • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6712D UNIT µs DESCRIPTION SYSCLK2 selected [default] Derived from CLKIN SYSCLK3 selected [default]. To select ECLKIN as source: EKSRC = 1 (DEVCFG.[4]) and...

  • Page 48: Clock Signal

    TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 PLL and PLL controller (continued) Table 27. PLL Clock Frequency Ranges CLOCK SIGNAL CLOCK SIGNAL PLLREF (PLLEN = 1) PLLOUT SYSCLK1 SYSCLK3 (EKSRC = 0) † SYSCLK2 rate must be exactly half of SYSCLK1.
  • Page 49 Divider D0 and PLL are bypassed. SYSCLK1/SYSCLK2/SYSCLK3 are divided down directly from input reference clock. Divider D0 and PLL are not bypassed. SYSCLK1/SYSCLK2/SYSCLK3 are divided down from PLL output. • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6712D Reserved PLLPWRDN PLLEN R/W−0 R/W−0b RW−0...
  • Page 50 TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 PLL and PLL controller (continued) PLLM Register (0x01B7 C110) 28 27 12 11 Reserved R−0 Legend: R = Read only, R/W = Read/Write; -n = value after reset Table 29.
  • Page 51 10010 = 10011 = 10100 = 10101 = 10110 = 10111 = 11000 = 11001 = 11010 = 11011 = 11100 = 11101 = 11110 11111 • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6712D 20 19 PLLDIVx R/W−x xxxx †...
  • Page 52 TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 PLL and PLL controller (continued) OSCDIV1 Register (0x01B7 C124) 28 27 12 11 OD1EN Reserved R/W−1 Legend: R = Read only, R/W = Read/Write; -n = value after reset The OSCDIV1 register controls the oscillator divider 1 for CLKOUT3.

  • Page 53: General-Purpose Input/Output (Gpio)

    SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 24 23 Reserved R/W-1 R/W-1 R/W-1 24 23 Reserved R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6712D — — — R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 — — — R/W-0 R/W-0 R/W-0 R/W-0...

  • Page 54: Power-Down Mode Logic

    TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 power-down mode logic Figure 11 shows the power-down mode logic. Clock CLKIN † External input clocks, with the exception of CLKOUT3 and CLKIN, are not gated by the power-down mode logic.
  • Page 55 PD2 and PD3 modes can only be aborted by device reset. Table 32 summarizes all the power-down modes. FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 R/W-0 R/W-0 • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6712D R/W-0...

  • Page 56: Power Down Mode

    TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 Table 32. Characteristics of the Power-Down Modes PRWD FIELD POWER-DOWN (BITS 15−10) MODE 000000 No power-down 001001 Wake by an enabled interrupt Wake by an enabled or...

  • Page 57: Power-Supply Decoupling

    FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 DV DD Schottky Diode C6000 CV DD V SS Figure 13. Schottky Diode Diagram • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6712D...

  • Page 58: Ieee 1149.1 Jtag Compatibility Statement

    DSP or exercise the DSP’s boundary scan functionality. The TMS320C6712D DSP includes an internal pulldown (IPD) on the TRST pin to ensure that TRST will always be asserted upon power up and the DSP’s internal emulation logic will always be properly initialized when this pin is not routed out.

  • Page 59: Emif Device Speed

    143 MHz 32-bit SDRAM (−7) 166 MHz 32-bit SDRAM (−6) 183 MHz 32-bit SDRAM (−55) 200 MHz 32-bit SDRAM (−5) • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6712D MAXIMUM ACHIEVABLE MAXIMUM ACHIEVABLE EMIF-SDRAM INTERFACE SPEED 100 MHz For short traces, SDRAM data...

  • Page 60: Emif Big Endian Mode Correctness

    TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 EMIF big endian mode correctness The device Endian mode pin (LENDIAN) selects the endian mode of operation (little endian or big endian) for the device. Little endian is the default setting.

  • Page 61: Absolute Maximum Ratings Over Operating Case Temperature Range

    ..........• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6712D † − 0.3 V to 1.8 V −0.3 V to 4 V −0.3 V to DV...

  • Page 62: Electrical Characteristics Over Recommended Ranges Of Supply Voltage And Operating Case Temperature

    TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 electrical characteristics over recommended ranges of supply voltage and operating case † temperature (unless otherwise noted) PARAMETER High-level output All signals except CLKS1 and V OH...

  • Page 63: Parameter Measurement Information

    Tester Pin Electronics Transmission Line Z0 = 50 Ω (see note) MAX and V • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6712D Data Sheet Timing Reference Point Output Under Test Device Pin (see note) V ref = 1.5 V...
  • Page 64 TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 PARAMETER MEASUREMENT INFORMATION (CONTINUED) AC transient rise/fall time specifications Figure 18 and Figure 19 show the AC transient specifications for Rise and Fall Time. For device-specific information on these values, refer to the Recommended Operating Conditions section of this Data Sheet.

  • Page 65: Timing Parameters And Board Routing Analysis

    TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 timing parameters and board routing analysis The timing parameter values specified in this data sheet do not include delays by board routings. As a good board design practice, such delays must always be taken into account. Timing values may be adjusted by increasing/decreasing such delays.
  • Page 66 TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 PARAMETER MEASUREMENT INFORMATION (CONTINUED) Table 34. Board-Level Timings Example (see Figure 20) ECLKOUT (Output from DSP) ECLKOUT (Input to External Device) Control Signals † (Output from DSP)

  • Page 67: Input And Output Clocks

    INPUT AND OUTPUT CLOCKS (see Figure 21) Figure 21. CLKIN Timings PARAMETER PARAMETER Figure 22. CLKOUT2 Timings • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6712D −150 PLL MODE BYPASS MODE UNIT (PLLEN = 1) (PLLEN = 0) 83.3 0.4C 0.4C...
  • Page 68 TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 INPUT AND OUTPUT CLOCKS (CONTINUED) switching characteristics over recommended operating conditions for CLKOUT3 (see Figure 23) t c(CKO3) Cycle time, CLKOUT3 t w(CKO3H) Pulse duration, CLKOUT3 high...
  • Page 69 FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 PARAMETER PARAMETER Figure 25. ECLKOUT Timings • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6712D †‡§ −150 UNIT UNIT E − 0.9 E + 0.9 EH − 0.9 EH + 0.9...

  • Page 70: Asynchronous Memory Timing

    TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 ASYNCHRONOUS MEMORY TIMING timing requirements for asynchronous memory cycles t su(EDV-AREH) Setup time, EDx valid before ARE high t h(AREH-EDV) Hold time, EDx valid after ARE high...
  • Page 71 Figure 26. Asynchronous Memory Read Timing FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 Strobe = 3 Not Ready Address Read Data • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6712D Hold = 2...
  • Page 72 TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 ASYNCHRONOUS MEMORY TIMING (CONTINUED) Setup = 2 ECLKOUT BE[3:0] EA[21:2] ED[31:0] AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † ARDY † AOE/SDRAS/SSOE, ARE/SDCAS/SSADS, and AWE/SDWE/SSWE operate as AOE (identified under select signals), ARE, and AWE, respectively, during asynchronous memory accesses.

  • Page 73: Synchronous-Burst Memory Timing

    ‡ ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses. FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 † (see Figure 28) PARAMETER PARAMETER • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6712D −150 UNIT UNIT −150 UNIT UNIT...
  • Page 74 TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED) ECLKOUT CE[3:0] BE[1:0] EA[21:2] ED[15:0] ARE/SDCAS/SSADS † AOE/SDRAS/SSOE † AWE/SDWE/SSWE † † ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses.

  • Page 75: Synchronous Dram Timing

    ‡ ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 SYNCHRONOUS DRAM TIMING † (see Figure 30) PARAMETER PARAMETER • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6712D -150 UNIT UNIT −150 UNIT UNIT...
  • Page 76 TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 SYNCHRONOUS DRAM TIMING (CONTINUED) READ ECLKOUT CE[3:0] BE[1:0] Bank EA[21:13] EA[11:2] Column EA12 ED[15:0] AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † † ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses.
  • Page 77 † ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 WRITE Bank Column Figure 31. SDRAM Write Command • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6712D...
  • Page 78 TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 SYNCHRONOUS DRAM TIMING (CONTINUED) ECLKOUT CE[3:0] BE[1:0] EA[21:13] EA[11:2] EA12 ED[15:0] AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † † ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses.
  • Page 79 † ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 DEAC Bank Figure 34. SDRAM DEAC Command REFR Figure 35. SDRAM REFR Command • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6712D...
  • Page 80 TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 SYNCHRONOUS DRAM TIMING (CONTINUED) ECLKOUT CE[3:0] BE[1:0] EA[21:2] ED[15:0] AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † † ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses.

  • Page 81: Hold/Holda Timing

    SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 HOLD/HOLDA TIMING † (see Figure 37) PARAMETER PARAMETER External Requestor Owns Bus Figure 37. HOLD/HOLDA Timing • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6712D −150 UNIT UNIT †‡ −150 UNIT UNIT § DSP Owns Bus C6712D...

  • Page 82: Busreq Timing

    TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 switching characteristics over recommended operating conditions for the BUSREQ cycles (see Figure 38) t d(EKOH-BUSRV) Delay time, ECLKOUT high to BUSREQ valid ECLKOUT BUSREQ BUSREQ TIMING...

  • Page 83: Reset Timing

    FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 RESET TIMING (see Figure 39) CLKMODE0 = 1 • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6712D −150 UNIT UNIT ¶ (see Figure 39) −150 UNIT UNIT...
  • Page 84 TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 Phase 1 CLKIN ECLKIN RESET Internal Reset Internal SYSCLK1 Internal SYSCLK2 Internal SYSCLK3 ECLKOUT CLKOUT2 CLKOUT3 EMIF Z Group † EMIF Low Group † Z Group †...

  • Page 85: External Interrupt Timing

    † P = 1/CPU clock frequency in ns. For example, when running parts at 100 MHz, use P = 10 ns. EXT_INT, NMI Figure 40. External/NMI Interrupt Timing FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 EXTERNAL INTERRUPT TIMING † (see Figure 40) • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6712D −150 UNIT UNIT...

  • Page 86: Multichannel Buffered Serial Port Timing

    TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293 − OCTOBER 2005 MULTICHANNEL BUFFERED SERIAL PORT TIMING timing requirements for McBSP t c(CKRX) Cycle time, CLKR/X t w(CKRX) Pulse duration, CLKR/X high or CLKR/X low t su(FRH-CKRL) t su(FRH-CKRL) Setup time, external FSR high before CLKR low...
  • Page 87 CLKX int CLKX ext CLKX int CLKX ext FSX int FSX ext • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6712D SPRS293 − OCTOBER 2005 †‡ (see Figure 41) −150 UNIT UNIT 2P §¶ C − 1 # C + 1 # −2...
  • Page 88 TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293 − OCTOBER 2005 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKS CLKR FSR (int) FSR (ext) CLKX FSX (int) FSX (ext) FSX (XDATDLY=00b) Bit 0 Bit(n-1) (n-2) Bit(n-1) (n-2) Figure 41. McBSP Timings •...
  • Page 89 ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. FLOATING POINT DIGITAL SIGNAL PROCESSOR • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6712D SPRS293 − OCTOBER 2005 −150 UNIT UNIT †‡...
  • Page 90 TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293 − OCTOBER 2005 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0 PARAMETER PARAMETER Hold time, FSX low t h(CKXL-FXL) after CLKX low ¶...
  • Page 91 FLOATING POINT DIGITAL SIGNAL PROCESSOR †‡ (see Figure 44) Bit(n-1) (n-2) Bit(n-1) • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6712D SPRS293 − OCTOBER 2005 −150 MASTER § SLAVE UNIT UNIT L − 2 L + 3 T − 2 T + 3 −3...
  • Page 92 TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293 − OCTOBER 2005 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1 t su(DRV-CKXH) Setup time, DR valid before CLKX high...
  • Page 93 # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). FLOATING POINT DIGITAL SIGNAL PROCESSOR Bit(n-1) (n-2) Bit(n-1) (n-2) †‡ (see Figure 46) • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6712D SPRS293 − OCTOBER 2005 (n-3) (n-4) (n-3) (n-4) †‡ (see Figure 46) −150 MASTER SLAVE UNIT UNIT 2 −...
  • Page 94 TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293 − OCTOBER 2005 CLKX Bit 0 Bit 0 Figure 46. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 Bit(n-1) Bit(n-1) • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443...

  • Page 95: Timer Timing

    FLOATING POINT DIGITAL SIGNAL PROCESSOR TIMER TIMING † (see Figure 47) PARAMETER PARAMETER Figure 47. Timer Timing • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6712D SPRS293 − OCTOBER 2005 −150 UNIT UNIT † −150 UNIT UNIT 4P −3 4P −3...

  • Page 96: General-Purpose Input/Output (Gpio) Port Timing

    TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293 − OCTOBER 2005 GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORT TIMING timing requirements for GPIO inputs t w(GPIH) Pulse duration, GPIx high t w(GPIL) Pulse duration, GPIx low † P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.

  • Page 97: Jtag Test-Port Timing

    Delay time, TCK low to TDO valid TDI/TMS/TRST FLOATING POINT DIGITAL SIGNAL PROCESSOR JTAG TEST-PORT TIMING PARAMETER PARAMETER Figure 49. JTAG Test-Port Timing • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6712D SPRS293 − OCTOBER 2005 −150 UNIT UNIT −150 UNIT UNIT...

  • Page 98: Mechanical Data

    TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS293 − OCTOBER 2005 package thermal resistance characteristics The following tables show the thermal resistance characteristics for the GDP and ZDP mechanical packages. thermal resistance characteristics (S-PBGA package) for GDP RΘ JC Junction-to-case Psi JT Junction-to-package top RΘ...

  • Page 99: Packaging Information

    www.ti.com PACKAGING INFORMATION Orderable Device Status TMS320C6712DGDP150 ACTIVE TMS320C6712DZDP150 ACTIVE The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs.

  • Page 100: Mechanical Data

    GDP (S–PBGA–N272) 27,20 26,80 24,20 23,80 A1 Corner 1,22 1,12 0,90 0,65 0,60 0,57 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MO-151 24,13 TYP 1,27 Bottom View 2,57 MAX Seating Plane 0,10...
  • Page 101 ZDP (S–PBGA–N272) 27,20 26,80 24,20 23,80 A1 Corner 1,22 1,12 0,90 0,65 0,60 0,57 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MO-151 D. This package is lead-free. 24,13 TYP 1,27 Bottom View...

  • Page 102: Important Notice

    TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions:...

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