Standard Operation For Cpu Maskable Interrupts - Texas Instruments TMS320C28x Reference Manual

Standard Operation for Maskable Interrupts
Figure 3−4. Standard Operation for CPU Maskable Interrupts
3-12
Interrupt request sent to CPU
Set corresponding IFR flag bit.
No
Interrupt enabled in
Yes
No
Interrupt enabled by
INTM bit?
Yes
Clear corresponding IFR bit.
Empty pipeline.
Increment and temporarily store PC.
Fetch interrupt vector.
Increment SP by 1.
Perform automatic context save.
Clear corresponding IER bit.
Set INTM and DBGM. Clear LOOP,
EALLOW, and IDLESTAT.
Load PC with fetched vector.
Execute interrupt service routine.
Program continues
IER?
protected from interrupts
This sequence