Texas Instruments TMS320C28x Reference Manual page 681

Glossary
V
W
Z
V bit (overflow flag): A bit in status register ST0 that indicates when the re-
sult of an operation causes an overflow in the location holding the result
(V = 1). If no overflow occurs, V is not modified.
vector: See interrupt vector.
vector location: See interrupt vector location.
vector map (VMAP) bit: A bit in status register ST1 that determines the ad-
dresses to which the interrupt vectors are mapped. When VMAP = 0, the
interrupt vectors are mapped to addresses 00 0000
gram memory. When VMAP = 1, the vectors are mapped to addresses
3F FFC0 −3F FFFF
16
vector table: See interrupt vector table.
W phase: See write (W) phase.
wait state: A cycle during which the CPU waits for a memory or peripheral
device to be ready for a read or write operation.
watchpoint: A place in a routine where it is to be halted if an address or an
address and data combination match specified compare values. When
a watchpoint is reached, the routine is halted and the CPU enters the de-
bug-halt state.
word: In this document, a word is 16 bits unless specifically stated to be
otherwise.
write (W) phase: The last of eight pipeline phases an instruction passes
through. In this phase, if a value or result is to be written to memory, the
CPU sends to memory the destination address and the data to be written.
See also pipeline phases.
zero fill: Fill the unused low- and/or high-order bits of a value with 0s.
zero flag (Z): A bit in status register ST0 that indicates when the result of an
operation is 0 (Z = 1).
in program memory.
16
−00 003F in pro-
16 16