Benchmark Counter/Event Counter(S) - Texas Instruments TMS320C28x Reference Manual

Analysis Breakpoints, Watchpoints, and Counter(s)

7.7.3 Benchmark Counter/Event Counter(s)

7-20
When comparing two addresses, you can set two watchpoints. When comparing
an address and a data value, you can set only one watchpoint. When performing
a read watchpoint, the address is available a few cycles earlier than the data; the
watchpoint logic accounts for this.
The point where execution stops depends on whether the watchpoint was a
read or write watchpoint, and whether it was an address or an address/data
read watchpoint. In the following example, a read address watchpoint occurs
when the address X is accessed, and the CPU stops with the instruction count-
er (IC) pointing three instructions after that point:
MOV AR4,#X
MOV AL,*+AR4[0]
nop
nop
nop
For a read watchpoint that requires both an address and data match, the CPU
stops with the IC pointing six instructions after that point:
MOV AR4,#X
MOV AL,*+AR4[0]
nop
nop
nop
nop
nop
nop
In the following example, a write address watchpoint occurs when the address
Y is accessed, and the CPU stops with the IC pointing six instructions after that
point:
MOV AR4,#Y
MOV *+AR4[0],AL
nop
nop
nop
nop
nop
nop
The 40-bit performance counter on the C28x can be used as a benchmark
counter to increment every CPU clock cycle (it can be configured not to count
when the CPU is in the debug-halt state). Wait states affect the counter. Wait
states in the read 1 and write pipeline phases of an executing instruction affect
the counter, regardless of whether an instruction is being single-stepped or
run. However, wait states in the fetch 1 pipeline phase do not affect the counter
during single-stepping, because the cycle counting does not begin until the de-
; Data read
; The IC will point here
; Data read
; The IC will point here
; Data write
; The IC will point here