Texas Instruments TMS320C28x Reference Manual page 504

SUBCUL ACC,loc32
SYNTAX OPTIONS
SUBCUL ACC,loc32
Operands ACC
loc32
Description
Flags and Z
Modes
N
C
Repeat
0101 0110 0001 0111
0000 0000 LLLL LLLL
Accumulator register
Addressing mode (see Chapter 5)
Perform 32-bit conditional subtraction, which can be used for unsigned
modulus division:
temp(32:0) = ACC << 1 + P(31) − [loc32];
if( temp(32:0) >= 0 )
ACC = temp(31:0);
P = (P << 1) + 1;
else
ACC:P = ACC:P << 1;
To perform 32-bit unsigned modulus division, the ACC register is zeroed and
the P register is loaded with the "Numerator" value prior to executing the
SUBCUL instruction. The value pointed to be the "loc32" addressing mode
contains the "Denominator" value. After executing the SUBCUL instruction
32 times, the ACC register will contain the "Remainder" and the P register will
contain the "Quotient" results. To perform signed modulus division, the
"Numerator" and "Denominator" values must be converted to unsigned
quantities, before executing the SUBCUL instruction. The final "Quotient"
result must be negated if the "Numerator" and "Denominator" values were of
different sign else the quotient is left unchanged.
At the end of the operation, the Z flag is set if the ACC value is zero, else Z is
cleared. The calculation of temp(32:0) has no effect on the Z bit.
At the end of the operation, the N flag is set if bit 31 of the ACC is 1, else N is
cleared. The calculation of temp(32:0) has no effect on the N bit.
If the calculation of temp(32:0) generates a borrow, C is cleared; otherwise C
is set.
Note: The V and OVC flags are not affected by the operation.
If this operation is repeated, then the instruction will be executed N+1 times.
The state of the Z, N, C flags will reflect the final result. The V flag will be set if
an intermediate overflow occurs. The OVC flag will count intermediate
overflows, if overflow mode is disabled.
Subtract Conditional 32 Bits
OPCODE OBJMODE
SUBCUL ACC,loc32
RPT CYC
1 Y N+1
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