Texas Instruments TMS320C28x Reference Manual page 520

TRAP #VectorNumber
SYNTAX OPTIONS
TRAP #VectorNumber
Operands Vector
Number
Description
Vector Interrupt
Number Vector
0 RESET
1 INT1
2 INT2
3 INT3
4 INT4
5 INT5
6 INT6
7 INT7
8 INT8
9 INT9
10 INT10
11 INT11
12 INT12
13 INT13
14 INT14
15 DLOGINT
0000 0000 001C CCCC
CPU interrupt vector 0 to 31
The TRAP instruction transfers program control to the interrupt service
routine that corresponds to the vector specified in the instruction. It does
not affect the interrupt flag register (IFR) or the interrupt enable register
(IER), regardless of whether the chosen interrupt has corresponding bits in
these registers. The TRAP instruction is not affected by the interrupt global
mask bit (INTM) in status register ST1. It also not affected by the enable bits
in the IER or the debug interrupt enable register (DBGIER). Once the TRAP
instruction reaches the decode phase of the pipeline, hardware interrupts
cannot be serviced until the TRAP instruction is done executing (until the
interrupt service routine begins).
The following table indicates which interrupt vector is associated with a
chosen value for the VectorNumber operand:
Vector
Number
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
OPCODE OBJMODE
Interrupt
Vector
RTOSINT
Reserved
NMI
ILLEGAL
USER1
USER2
USER3
USER4
USER5
USER6
USER7
USER8
USER9
USER10
USER11
USER12
TRAP #VectorNumber
Software Trap
RPT CYC
X − 8
6-363