Table of Contents
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Understanding
the Computer Module
The Function Cards
Serial Distribution
Network
This is a serial digital network for communication between bedside monitors and central
stations, for example, arrhythmia computers. The data is passed, over a two wire bus, in
a similar way to the message passing bus within the system. Each data type has its own
associated "signature". This is so the equipment does not need to know which other equipment
will use the information. Any equipment wishing to use the information from the SDN,
including the Component Central Monitor, can choose the data it requires using the data
signature.
All communications within the SDN, are controlled by the System Communication Controller or
SCC which is located at the center of the SDN star configuration. This instructs the monitors on
the branches of the SDN when they can send and receive data to and from the network using a
32ms poll cycle. The poII cycle is divided into 4ms dead time and 28ms for passing data to and
from the network.
SDN Interface
Connection
The SDN interface card must be connected to a free branch of the SDN. In the event of an
SDN failure or the branch becoming disconnected from the SDN, the instruments on the same
branch can still communicate with each other using the autopoll circuitry in the SIC Chip along
with the priority wire. The last box detection circuitry checks for a downstream connection. If
there is no downstream connection, the line is terminated using a relay.
SDN Synchronization
The timing for the system is governed by the 32ms frame interrupt (Frame-Int). When an SDN
Interface is installed, then Frame-Int must be synchronized to the SDN-Sync on the UTIL-CPU,
which indicates the start of a 32ms poll cycle, for data transfer. Data can only be written to or
read from the SIC RAM when both Frame-SYNC and SDN-SYNC are low (during the 4ms dead
time).
Note
If there is no SDN Interface
card
installed, then the 32ms clock in the system is
free-running.
Data Transfer
All data for transmission on the SDN is placed into the SIC RAM by the UTIL-CPU in the 4ms
dead time. The SIC Chip then automatically sends the data over the SDN during the remaining
28ms period. Wait cycle logic guarantees the timing between the UTIL-CPU and the SIC Chip.
The UTIL-CPU can select SDN data by placing a signature for selected data in the SIGN-RAM.
Received data is placed in the other half of the SIC RAM and can be read by the UTIL-CPU
in the 4ms part of the poll cycle. -A clock, using a 28.8MHz oscillator, is generated by the
DATA-SYNC gate array
and
is used to synchronize incoming data. This gate array is then used
to guarantee that the sample clock is in the middle of the data clock when the data is stable.
DTCK is used to acknowledge a RAM-ACCESS command from the UTIL-CPU so the UTILXPU
can run on. There are no wait states necessary for access to the SIC,RAM, Identifier and the
4-bit Latch.
4-bit Latch
This is used by the UTIL-CPU to perform the following tasks:
bit 0 (databit8) Switches the control signals between the UTIL-CPU and the SIC Chip.
2.34
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Troubleshooting
