Analog Devices ADuCM356 Reference Manual
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Analog Devices ADuCM356 Reference Manual

Analog Devices ADuCM356 Reference Manual

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PREFACE

The ADuCM356 hardware reference manual published by Analog
Devices, Inc., employs the following terminology to indicate actions,
functions, and processes that are mandatory in ensuring that the
ADuCM356 performs to the standards established by the ISO
26262-2018:
Required, requires, requirement: indicates no other option.
►
Must: indicates an obligatory action.
►
Can: indicates a possible option.
►
May: indicates either optional or permissible, context dependent.
►
Should: a recommended condition or action that is not required
►
but that reflects best practice.
Comply, complies, compliance: meets specifications or other
►
requirements provided by a secondary source, such as a data
sheet.
Obligation: refers to the responsibility of the user, including a
►
potential legal responsibility.
Must not: refrain from taking an action or refrain from causing a
►
condition.
Do not: refrain from taking an action.
►

SCOPE

This reference manual provides a detailed description of the func-
tionality and features of the ADuCM356.
Full specifications on the
ADuCM356
data sheet. Consult the data sheet in conjunction with this reference
manual when working with this device. Refer to the ADuCM356
data sheet for the functional block diagram.
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS.
ADuCM356 Hardware Reference Manual
are available in the product
Reference Manual | ADuCM356
UG-2111
Rev. A | 1 of 312

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Summary of Contents for Analog Devices ADuCM356

  • Page 1: Preface

    Consult the data sheet in conjunction with this reference manual when working with this device. Refer to the ADuCM356 data sheet for the functional block diagram. PLEASE SEE THE LAST PAGE FOR AN IMPORTANT Rev.

  • Page 2: Table Of Contents

    ADuCM356 TABLE OF CONTENTS Preface..............1 Key Protection for PWRMOD and Scope..............1 SRAMRET Register........29 Using the ADuCM356 Hardware Reference Control for Retention SRAM During Manual..............9 Hibernate Mode Register....... 29 Number Notations..........9 High-Power Buck Control Register....30 Register Access Conventions......9 Control for SRAM Parity and Instruction ADuCM356 Overview..........
  • Page 3 Reference Manual ADuCM356 TABLE OF CONTENTS ADC Circuit Overview........53 Offset Calibration Voltage Channel (PGA ADC Circuit Features........53 Gain = 1) Register.......... 73 ADC Circuit Operation........54 Gain Calibration Voltage Input Channel ADC Transfer Function........54 (PGA Gain = 1) Register........ 73 ADC Low-Power Current Input Channels ..55...
  • Page 4 Reference Manual ADuCM356 TABLE OF CONTENTS Low-Power TIA Switch Configuration for DAC Offset with Attenuator Enabled (High- Channel 1 Register.........93 Power Mode) Register........110 LPDAC0 Data Out Register......94 DAC Offset with Attenuator Disabled (High- LPDAC0 Switch Control Register.....94 Power Mode) Register........111 LPDAC0 Control Register........
  • Page 5 IRQ Abort Enable (Upper Bits) Register..197 Register............176 ECC Configuration Register......197 Channel Bytes Swap Enable Set Register..176 ECC Status (Address) Register......199 Channel Bytes Swap Enable Clear Register..176 Analog Devices Flash Security Register..199 analog.com Rev. A | 5 of 312...
  • Page 6 Register Summary: System (Digital Die)... 206 C Operating Modes........223 Register Details: System (Digital Die)....207 Register Summary: I C........226 Analog Devices Identification (Digital Die) Register Details: I C.......... 227 Register............207 Initiator Control Register.........227 Chip Identifier (Digital Die) Register....207 Initiator Status Register........
  • Page 7 Reference Manual ADuCM356 TABLE OF CONTENTS SPI and Power-Down Modes......242 16-Bit Synchronous Load Value Registers..268 Register Summary: SPI0/SPI1......243 16-Bit Timer Synchronous Value Registers..268 Register Details: SPI0/SPI1.......244 Control Registers..........268 Status Registers..........244 Clear Interrupt Registers........ 269 Receive Registers.......... 245 Capture Registers..........
  • Page 8 Reference Manual ADuCM356 TABLE OF CONTENTS Digital Die Wake-Up Timer........ 287 Snapshot 2 Register........298 Overview............287 Modulo Register..........299 Features............287 Count 2 Register..........299 Regular and Periodic Modulo 60 Interrupts..287 Alarm 2 Register..........301 Timer Matching Alarm Value Interrupts..287 Status 6 Register..........301...

  • Page 9: Using The Aducm356 Hardware Reference Manual

    Reference Manual ADuCM356 USING THE ADUCM356 HARDWARE REFERENCE MANUAL NUMBER NOTATIONS Table 1. Number Notations Notation Description Bit N Bits are numbered in little endian format, where the least significant bit of a number is referred to as Bit 0.

  • Page 10: Aducm356 Overview

    Hardware accelerators, including digital discrete Fourier trans- ► A low cost development system and a third party compiler and form (DFT) calculations. emulator tool support are included in the ADuCM356 evaluation kit. Digital-to-Analog Converters (DACs) Applications The device has the following DACs related features:...
  • Page 11 Reference Manual ADuCM356 ADUCM356 OVERVIEW Figure 1. Arm Cortex-M3 Memory Map Diagram analog.com Rev. A | 11 of 312...

  • Page 12: Clocking Architecture

    CLKCON0, Bits[5:0], which allows CLOCKING ARCHITECTURE OPERATION reduced power consumption. The ADuCM356 contains two internal dice. Therefore, there are The system performance of the analog die has only been validated two independent clock systems: a digital die clock system and with the system clock = 16 MHz.

  • Page 13: Clock Gating

    Reference Manual ADuCM356 CLOCKING ARCHITECTURE bond wire connecting this AFE die pad to the digital die pad, P1.10, on the digital die that can be configured as the external clock input for the digital die. To connect and select the AFE die 16 MHz oscillator as the external clock input for the digital die, perform the following steps: 1.
  • Page 14 Reference Manual ADuCM356 CLOCKING ARCHITECTURE To exit hibernate mode to switch back to using only the AFE clock, use the following suggested sequence: uiDummyRead = pADI_AFE->LPDACCON0; // Dummy read to wake-up AFE die delay_10us(2000); // Wait 20mS DigClkSel(DIGCLK_SOURCE_AFE); UrtCfg(pADI_UART0,B57600, // Re-In►...

  • Page 15: Register Summary: Clock Architecture

    Reference Manual ADuCM356 REGISTER SUMMARY: CLOCK ARCHITECTURE Table 3. Digital Die System Clock Register Summary (CLKG0_CLK Stack) Address Name Description Reset Access 0x4004C10C Key protection for CTL register 0x00000000 0x4004C110 Oscillator control 0x00000302 0x4004C300 CTL0 Clock Control 0 0x00000078 0x4004C304...

  • Page 16: Register Details: Clock Architecture

    Reference Manual ADuCM356 REGISTER DETAILS: CLOCK ARCHITECTURE KEY PROTECTION FOR CTL REGISTER Address: 0x4004C10C, Reset: 0x00000000, Name: KEY Table 5. Bit Descriptions for KEY Bits Bit Name Settings Description Reset Access [31:16] Reserved Reserved. 0x0000 [15:0] VALUE 0xCB14 Oscillator Key. The CTL register is key protected. To unlock this protection, write 0xCB14 to KEY before 0x0000 writing to CTL.

  • Page 17: Clock Dividers Register

    Reference Manual ADuCM356 REGISTER DETAILS: CLOCK ARCHITECTURE CLOCK DIVIDERS REGISTER Address: 0x4004C304, Reset: 0x00100404, Name: CTL1 The clock dividers register is used to set the divide rates for the HCLK, PCLK, and ACLK dividers. This register can be written to at any time. All unused bits are read only, returning a value of 0.

  • Page 18: Clocking Status Register

    Reference Manual ADuCM356 REGISTER DETAILS: CLOCK ARCHITECTURE Table 9. Bit Descriptions for CTL5 (Continued) Bits Bit Name Settings Description Reset Access disable this bit to control ACLK out. Before programming the ACLKDIVCNT bits in the CTL1 register, clear this bit to 0. Otherwise, the ACLKDIVCNT bit is not taken into effect.

  • Page 19: Clock Gate Enable Register

    Reference Manual ADuCM356 REGISTER DETAILS: CLOCK ARCHITECTURE Table 11. Bit Descriptions for CLKCON0 Bits Bit Name Settings Description Reset Access [15:6] Reserved Reserved. Do not write to this bit. [5:0] SYSCLKDIV System Clock Divider Configuration. The system clock divider is used to provide a divided clock from the root clock, which drives the peripheral bus, die to die interface, and most digital peripherals.

  • Page 20: Gpio Clock Mux Select To Gpio1 Pin Register

    Reference Manual ADuCM356 REGISTER DETAILS: CLOCK ARCHITECTURE Table 13. Bit Descriptions for CLKSEL (Continued) Bits Bit Name Settings Description Reset Access 1 External high frequency crystal (XTAL) clock. 10 Internal low frequency oscillator clock. Not recommended. 11 External clock. [1:0] SYSCLKSEL Select System Clock Source.

  • Page 21: Key Protection For Osccon Register

    Reference Manual ADuCM356 REGISTER DETAILS: CLOCK ARCHITECTURE Table 16. Bit Descriptions for CLKEN0 (Continued) Bits Bit Name Settings Description Reset Access SLPWUTDIS Sleep and Wake-Up Timer Clock Disable. 0 Turn on sleep wake-up timer clock. 1 Turn off sleep wake-up timer clock.

  • Page 22: High-Power Oscillator Configuration Register

    Reference Manual ADuCM356 REGISTER DETAILS: CLOCK ARCHITECTURE Table 18. Bit Descriptions for OSCCON (Continued) Bits Bit Name Settings Description Reset Access 1 The low frequency oscillator is enabled. HIGH-POWER OSCILLATOR CONFIGURATION REGISTER Address: 0x400C20BC, Reset: 0x00000024, Name: HPOSCCON Table 19. Bit Descriptions for HPOSCCON...

  • Page 23: Power Management Unit

    Figure 3. Power Supply Architecture Block Diagram POWER MANAGEMENT UNIT FEATURES Active Mode The ADuCM356 contains two separate PMUs, one for each die. The Arm Cortex-M3 is executing from flash and SRAM on the The PMUs control the different power modes of each ADuCM356 digital die.

  • Page 24: Code Examples

    1.6 V. //Close switches NL and NL2. PSWFULL► CON[11:10]= [11]b When the ADuCM356 wakes up from any of the low-power modes, pADI_AFE-> PSWFULLCON|=0x6C00; // Close the device returns to Mode 0. PL2, PL1, P12, P11 switches to tie HSTIA N and Flexi Mode, Mode 1 (Digital Die Only) //terminals to 1.8 V LDO...

  • Page 25: Monitor Voltage Control

    The user code must monitor the chip power supply voltages. The sleep mode value AFE die peripherals are not specified to operate at voltages <2.8 V. The ADuCM356 provides a number of features to help user code iMode = 0; monitor the AVDD and DVDD supply rails of the ADuCM356.
  • Page 26 AVDD_REG regulated 1.8 V analog supply voltage. ► The analog die has its own POR circuit that generates a full chip reset if the supply voltage drops below its brownout voltage. Refer to the ADuCM356 data sheet for details. analog.com Rev. A | 26 of 312...

  • Page 27: Register Summary: Power Management Unit

    Reference Manual ADuCM356 REGISTER SUMMARY: POWER MANAGEMENT UNIT Table 21. Digital Die Power Management Register Summary (PMG0 Stack) Address Name Description Reset Access 0x4004C000 Power supply monitor interrupt enable 0x00000000 0x4004C004 PSM_STAT Power supply monitor status 0x2100 0x4004C008 PWRMOD Power mode...

  • Page 28: Register Details: Power Management Unit

    Reference Manual ADuCM356 REGISTER DETAILS: POWER MANAGEMENT UNIT POWER SUPPLY MONITOR INTERRUPT ENABLE REGISTER Address: 0x4004C000, Reset: 0x00000000, Name: IEN Table 23. Bit Descriptions for IEN Bits Bit Name Settings Description Reset Access [31:11] Reserved Reserved. 0x00000 IENBAT Interrupt Enable for AVDD_DD Range. Set this bit if an interrupt must be generated for the RANGEBAT bit.

  • Page 29: Power Mode Register

    Reference Manual ADuCM356 REGISTER DETAILS: POWER MANAGEMENT UNIT Table 24. Bit Descriptions for PSM_STAT (Continued) Bits Bit Name Settings Description Reset Access RANGE1 AVDD_DD Range 1 (>2.75 V). This is a write one to clear status bit indicating the relevant R/W1C AVDD_DD range.

  • Page 30: High-Power Buck Control Register

    Reference Manual ADuCM356 REGISTER DETAILS: POWER MANAGEMENT UNIT Table 27. Bit Descriptions for SRAMRET Bits Bit Name Settings Description Reset Access [31:2] Reserved Reserved. BNK2EN Enable Retention Bank 2 (16 kB). Bank address is 0x10000000 to 0x10003FFF if SRAM_CTL, Bit 31 = 1.

  • Page 31: Initialization Status Register

    Reference Manual ADuCM356 REGISTER DETAILS: POWER MANAGEMENT UNIT Table 29. Bit Descriptions for SRAM_CTL (Continued) Bits Bit Name Settings Description Reset Access PENBNK0 Enable Parity Check for SRAM Bank 0. SRAM Address 0x20000000 to Address 0x20001FFF. Parity is checked when data is read and when a byte or half word data is written to this SRAM area. If a parity error is detected, a bus error is generated and the execution vectors to the bus fault interrupt.

  • Page 32: Power Modes Register

    Reference Manual ADuCM356 REGISTER DETAILS: POWER MANAGEMENT UNIT Table 30. Bit Descriptions for SRAM_INITSTAT (Continued) Bits Bit Name Settings Description Reset Access 0 Not initialized. 1 Initialization completed. BNK1 Initialization Status of SRAM Bank 1. 0 Not initialized. 1 Initialization completed.

  • Page 33: Arm Cortex-M3 Processor

    ► A flexible RTC that supports a wide range of wake-up times. ► The ADuCM356 only supports the serial wire interface via the Three general-purpose timers and one watchdog timer. ► SWCLK and SWDIO pins. The device does not support the 5-wire, Programmable GPIOs, each with optional input interrupt capabili- ►...

  • Page 34: Arm Cortex-M3 Processor Related Documents

    Reference Manual ADuCM356 ARM CORTEX-M3 PROCESSOR ARM CORTEX-M3 PROCESSOR RELATED DOCUMENTS The following list contains documentation related to the Arm Cortex- Arm Cortex-M3 Processor Technical Reference Manual Revision ► r2p1 (DDI 0337) Arm Processor Cortex-M3 (AT420) and Cortex-M3 with ETM ►...

  • Page 35: System Resets

    This function effectively writes 0x05FA to the 16 MSBs of the Cortex register, AIRCR, Address 0xE000ED0C. Figure 4. Reset Sources of the ADuCM356 The NVIC_SystemReset() function, along with other useful func- tions, are defined in the Cortex microcontroller software interface...

  • Page 36: Register Summary: System Resets

    Reference Manual ADuCM356 REGISTER SUMMARY: SYSTEM RESETS Table 34. Digital Die Reset Register Summary Address Name Description Reset Access 0x4004C040 RST_STAT Digital die reset status 0x000000XX R/W1C Table 35. Always On Register Summary Address Name Description Reset Access 0x400C0A40 RSTSTA...

  • Page 37: Register Details: System Resets

    Reference Manual ADuCM356 REGISTER DETAILS: SYSTEM RESETS DIGITAL DIE RESET STATUS REGISTER Address: 0x4004C040, Reset: 0x000000XX, Name: RST_STAT Table 37. Bit Descriptions for RST_STAT Bits Bit Name Settings Description Reset Access [15:6] Reserved Reserved. [5:4] PORSRC POR Source for Digital Die. This bit contains additional details after a POR occurs.

  • Page 38: Programming, Protection, And Debug

    The ADuCM356 can also utilize the analog die watchdog timer for debugging. Disable the analog die watchdog timer when developing or debugging user code. Enable the timer only toward the end analog.com...

  • Page 39: System Exceptions And Peripheral Interrupts

    SYSTEM EXCEPTIONS AND PERIPHERAL INTERRUPTS peripherals. Table 40 lists the Arm Cortex-M3 processor system CORTEX-M3 AND FAULT MANAGEMENT exceptions. The ADuCM356 integrates an Arm Cortex-M3 processor, which supports several system exceptions and interrupts generated by Table 40. System Exceptions Exception Number Type Priority Description Reset −3 (highest)
  • Page 40 (0) is treated as fourth priority after a reset, an NMI, ble priorities. The default for all the programmable priorities is 0. or a hard fault. The ADuCM356 implements three priority bits, If the same priority level is assigned to two or more interrupts, analog.com...

  • Page 41: Interrupt Sources From The Analog Die

    Reference Manual ADuCM356 SYSTEM EXCEPTIONS AND PERIPHERAL INTERRUPTS their hardware priority (the lower the position number) determines Table 43 lists the registers to enable and disable relevant interrupts the order in which the processor activates them. For example, if and set the priority levels. The registers in...

  • Page 42: Clearing Analog Die Interrupt Sources

    Reference Manual ADuCM356 SYSTEM EXCEPTIONS AND PERIPHERAL INTERRUPTS if (uiIntSta & BITM_AFE_ADCINTSTA_ADCRDY) The following is an example interrupt service routine for the Analog Die General-Purpose Timer 0: szADCSamples[i]= AfeAdcRd(RAWADC); // AFE General-Purpose Timer0 Interrupt han► dler. void AfeGpTimer0_Int_Handler() CLEARING ANALOG DIE INTERRUPT ucSecondTimer = 1;...

  • Page 43: External Interrupt Configuration

    Reference Manual ADuCM356 SYSTEM EXCEPTIONS AND PERIPHERAL INTERRUPTS Table 43. NVIC Registers (Continued) Analog Devices Address Header File Name Description Access 0xE000E438 IPR14 IRQ56 to IRQ59 priority. 0xE000E43C IPR15 IRQ60 to IRQ63 priority. 0xE000ED00 CPUID CPU ID base. 0xE000ED04 ICSR Interrupt control and status.

  • Page 44: Register Summary: System Exceptions And Peripheral Interrupts

    Reference Manual ADuCM356 REGISTER SUMMARY: SYSTEM EXCEPTIONS AND PERIPHERAL INTERRUPTS Table 44. Digital Die External Interrupts Register Summary Address Name Description Reset Access 0x4004C080 XINT_CFG0 External Interrupt Configuration 0 0x00200000 0x4004C084 XINT_EXT_STAT External wake-up interrupt status 0x00000000 0x4004C090 XINT_CLR External interrupt clear...

  • Page 45: Register Details: System Exceptions And Peripheral Interrupts

    Reference Manual ADuCM356 REGISTER DETAILS: SYSTEM EXCEPTIONS AND PERIPHERAL INTERRUPTS EXTERNAL INTERRUPT CONFIGURATION 0 REGISTER Address: 0x4004C080, Reset: 0x00200000, Name: XINT_CFG0 Table 46. Bit Descriptions for XINT_CFG0 Bits Bit Name Settings Description Reset Access [31:24] Reserved Reserved. [23:21] UART_RX_MDE External Interrupt Using P0.11/UART_SIN Wake-Up Mode.

  • Page 46: External Wake-Up Interrupt Status Register

    Reference Manual ADuCM356 REGISTER DETAILS: SYSTEM EXCEPTIONS AND PERIPHERAL INTERRUPTS EXTERNAL WAKE-UP INTERRUPT STATUS REGISTER Address: 0x4004C084, Reset: 0x00000000, Name: XINT_EXT_STAT Table 47. Bit Descriptions for XINT_EXT_STAT Bits Bit Name Settings Description Reset Access [31:6] Reserved Reserved. STAT_UART_RXWKUP Interrupt Status Bit for P0.11/UART_SIN Wake-Up Interrupt. Read only register bit. Cleared by writing 1 to XINT_CLR, Bit 5.
  • Page 47 Reference Manual ADuCM356 REGISTER DETAILS: SYSTEM EXCEPTIONS AND PERIPHERAL INTERRUPTS Table 50. Bit Descriptions for EI2CON Bits Bit Name Settings Description Reset Access [15:4] Reserved Reserved. BUSINTEN Bus Interrupt Detection Enable Bit. Set before entering hibernate to enable the AFE wakeup via any analog die access.

  • Page 48: Analog Die Circuitry Summary

    Reference Manual ADuCM356 ANALOG DIE CIRCUITRY SUMMARY The ADuCM356 analog die includes the following eight main Use case configurations. The Use Case Configurations section ► blocks: describes typical electrochemical sensor use cases and the configuration of the ADuCM356 for each use case.
  • Page 49 Reference Manual ADuCM356 ANALOG DIE CIRCUITRY SUMMARY Figure 6. Block Level Overview of AFE Die Analog Circuitry and Connection to External Pins analog.com Rev. A | 49 of 312...

  • Page 50: Register Summary: Analog Die Circuitry

    Reference Manual ADuCM356 REGISTER SUMMARY: ANALOG DIE CIRCUITRY Table 51. Analog Die Circuitry Register Summary Address Name Description Reset Access 0x400C2000 AFECON Analog configuration 0x00080000 analog.com Rev. A | 50 of 312...

  • Page 51: Register Details: Analog Die Circuitry

    Reference Manual ADuCM356 REGISTER DETAILS: ANALOG DIE CIRCUITRY AFE CONFIGURATION REGISTER Address: 0x400C2000, Reset: 0x00080000, Name: AFECON Specific bits in these registers are relevant to particular blocks in the analog die. The relevant bits for each block are as follows: Bits relevant to the ADC block are Bit 16, Bit 15, Bit 13, Bit 12, Bit 8, Bit 7, and Bit 5.
  • Page 52 Reference Manual ADuCM356 REGISTER DETAILS: ANALOG DIE CIRCUITRY Table 52. Bit Descriptions for AFECON (Continued) Bits Bit Name Settings Description Reset Access EXBUFEN Enable Excitation Buffer on High-Speed DAC Output. 0 High-speed DAC excitation buffer disabled. 1 High-speed DAC excitation buffer enabled.

  • Page 53: Adc Circuit

    ADC CIRCUIT FEATURES ► measurements up to 200 kHz. This channel has dedicated TIAs The ADuCM356 includes a fast multichannel, 16-bit ADC. The input with a programmable gain resistor. multiplexer supports a number of external and internal channels. Multiple external voltage inputs.

  • Page 54: Adc Circuit Operation

    Reference Manual ADuCM356 ADC CIRCUIT The ADC has a number of postprocessing features, as follows: the mains power supply filter is enabled, the ADC update rate is typically 900 Hz. If no filtering is selected, the supported resolution Digital filtering of sinc2 and sinc3, and 50 Hz or 60 Hz power ►...

  • Page 55: Adc Low-Power Current Input Channels

    Reference Manual ADuCM356 ADC CIRCUIT To select the low-power TIA input channel for calibration and meas- ADC LOW-POWER CURRENT INPUT urement, refer to ADCCON, Bits[12:0] in Table 63. For low-power CHANNELS TIA0, the ADC positive input is selected by setting ADCCON,...
  • Page 56 Reference Manual ADuCM356 ADC CIRCUIT selected, and 400 kSPS or 160 kSPS if coming directly from the Sinc3 Filter sinc3 filter output. The input is the raw ADC codes at a rate of 800 kHz if the 16 MHz To enable the sinc2 filter, set AFECON, Bit 16 = 1. The output oscillator is selected on the analog die, or 1.6 MHz if the 32 MHz...

  • Page 57: Averaging, Statistics, And Outlier Detection Options

    Statistics Option The following code snippets demonstrate how to set up and use the The ADuCM356 supports the calculation of the mean value for a Temperature Sensor 0: programmable sample size of the sinc3 output. This calculation is controlled by the STATSCON register.

  • Page 58: Adc Initialization

    (VBE2). 3. Close all switches to connect all current sources to the VBE Because of the multiple input types of the ADuCM356, there are transistor and measure the VBE voltage to obtain VBE3. multiple offset and gain calibration options. The ADC must be...

  • Page 59: Adc Digital Signal Processor (Dsp) Built In Self Test

    ADCGAINGN9, ADCGNHSTIA When calibrating the gain error for the ADC voltage channels ADC DIGITAL SIGNAL PROCESSOR (DSP) during Analog Devices production testing, the value loaded to the BUILT IN SELF TEST ADCGAINGN1P5 calibration register is ≥0x4000. To ensure this It is possible to verify the digital logic blocks on the analog die value, the target ADC result is higher than normal.

  • Page 60: Voltage Reference Options

    Reference Manual ADuCM356 ADC CIRCUIT By completing the self test for a large number of digital waveform CRC result, all of the digital blocks shown in Figure 13 can be values, the CRC accelerator can compute a final CRC result. By checked for errors.

  • Page 61: Register Summary: Adc Circuit

    Reference Manual ADuCM356 REGISTER SUMMARY: ADC CIRCUIT Table 58. ADC Control Register Summary Address Name Description Reset Access 0x400C21A8 ADCCON ADC configuration register 0x00000000 0x400C2044 ADCFILTERCON ADC output filters configuration 0x00000301 0x400C2074 ADCDAT Raw result 0x00000000 0x400C2078 DFTREAL DFT result, real part...
  • Page 62 Reference Manual ADuCM356 REGISTER SUMMARY: ADC CIRCUIT Table 62. ADC Digital Logic Test Register Summary (Optional) Address Name Description Reset Access 0x400C0434 MKEY Key access for DSPUPDATEEN register 0x00000000 0x400C0438 DSPUPDATEEN Digital logic test enable 0x00000000 0x400C2374 TEMPCON1 Temperature Sensor 1 control 0x00020000 analog.com...

  • Page 63: Register Details: Adc Circuit

    Reference Manual ADuCM356 REGISTER DETAILS: ADC CIRCUIT ADC CONFIGURATION REGISTER Address: 0x400C21A8, Reset: 0x00000000, Name: ADCCON Table 63. Bit Descriptions for ADCCON Bits Bit Name Settings Description Reset Access [31:19] Reserved Reserved. [18:16] GNPGA PGA Gain Setup. 000 Gain = 1.

  • Page 64: Adc Output Filters Configuration Register

    Reference Manual ADuCM356 REGISTER DETAILS: ADC CIRCUIT Table 63. Bit Descriptions for ADCCON (Continued) Bits Bit Name Settings Description Reset Access 01000 AVDD/2. 01001 DVDD/2. 01010 AVDD_REG/2. 01011 Temperature Sensor 0 positive input. 01100 ADCVBIAS_CAP. 01101 DE0. 01110 SE0. 01111 SE1.

  • Page 65: Raw Result Register

    Reference Manual ADuCM356 REGISTER DETAILS: ADC CIRCUIT Table 64. Bit Descriptions for ADCFILTERCON (Continued) Bits Bit Name Settings Description Reset Access 1 Oversampling rate of 4. Use for 400 kHz sinc3 filter output update rate. Use when ADC update rate is 1.6 MSPS. High-power option.

  • Page 66: Dft Result, Real Part Register

    Reference Manual ADuCM356 REGISTER DETAILS: ADC CIRCUIT DFT RESULT, REAL PART REGISTER Address: 0x400C2078, Reset: 0x00000000, Name: DFTREAL Table 66. Bit Descriptions for DFTREAL Bits Bit Name Settings Description Reset Access [31:18] Reserved Reserved. [17:0] DATA DFT Real. DFT hardware accelerator returns a complex number. This register returns the 18-bit real part of the complex number from the DFT result.

  • Page 67: Analog Capture Interrupt Register

    Reference Manual ADuCM356 REGISTER DETAILS: ADC CIRCUIT Table 70. Bit Descriptions for ADCINTIEN (Continued) Bits Bit Name Settings Description Reset Access 1 Interrupt enabled. ADCMAXFAILIEN ADC Maximum Value Check Fail Interrupt Enable. When set, this bit generates an interrupt if the ADC result is greater than the value in the ADCMAX register.

  • Page 68: Afe Dsp Configuration Register

    Reference Manual ADuCM356 REGISTER DETAILS: ADC CIRCUIT Table 71. Bit Descriptions for ADCINTSTA (Continued) Bits Bit Name Settings Description Reset Access 1 Interrupt asserted. When set, indicates that ADCDAT result was greater than the value specified by the ADCMAX register. This bit generates an interrupt if ADCINTIEN, Bit 5 = 1. User must write 1 to this bit to clear it.

  • Page 69: Temperature Sensor 0 Configuration Register

    Reference Manual ADuCM356 REGISTER DETAILS: ADC CIRCUIT Table 72. Bit Descriptions for DFTCON (Continued) Bits Bit Name Settings Description Reset Access 100 DFT point number is 64. DFT uses 64 ADC samples. 101 DFT point number is 128. DFT uses 128 ADC samples.

  • Page 70: Number Of Repeat Adc Conversions Register

    Reference Manual ADuCM356 REGISTER DETAILS: ADC CIRCUIT Table 74. Bit Descriptions for BUFSENCON (Continued) Bits Bit Name Settings Description Reset Access 1 Close Switch. Close this switch to connect the 1.1 V reference to the discharging circuit. V1P1LPADCEN ADC 1.1 V Low-Power Common-Mode Buffer. Optional. Use either high-power or low-power reference buffer.

  • Page 71: Calibration Lock Register

    Reference Manual ADuCM356 REGISTER DETAILS: ADC CIRCUIT Table 76. Bit Descriptions for ADCBUFCON (Continued) Bits Bit Name Settings Description Reset Access 1 Disable chop. CHOPDIS Configure ADC Buffer Chop. 0 Enable chop. 1 Disable chop. CHOPDIS Configure PGA Chop. 0 Enable chop.

  • Page 72: Offset Calibration Low-Power Tia1 Channel Register

    Reference Manual ADuCM356 REGISTER DETAILS: ADC CIRCUIT Table 79. Bit Descriptions for ADCGNLPTIA0 (Continued) Bits Bit Name Settings Description Reset Access 0x0000 0. Invalid value. Results in an ADC result of 0. OFFSET CALIBRATION LOW-POWER TIA1 CHANNEL REGISTER Address: 0x400C22C0, Reset: 0x00000000, Name: ADCOFFSETLPTIA1 Table 80.

  • Page 73: Gain Calibration For High-Speed Tia Channel Register

    Reference Manual ADuCM356 REGISTER DETAILS: ADC CIRCUIT GAIN CALIBRATION FOR HIGH-SPEED TIA CHANNEL REGISTER Address: 0x400C2284, Reset: 0x00004000, Name: ADCGNHSTIA Table 83. Bit Descriptions for ADCGNHSTIA Bits Bit Name Settings Description Reset Access [31:15] Reserved Reserved. [14:0] VALUE Gain Error Calibration High-Speed TIA Channel.

  • Page 74: Gain Calibration Voltage Input Channel (Pga Gain = 1.5) Register

    Reference Manual ADuCM356 REGISTER DETAILS: ADC CIRCUIT Table 86. Bit Descriptions for ADCOFFSETGN1P5 Bits Bit Name Settings Description Reset Access [31:15] Reserved Reserved. [14:0] VALUE Offset Calibration Gain 1.5. ADC offset correction with PGA gain = 1.5. 0x3FFF 4095.75 (maximum positive offset calibration value).

  • Page 75: Offset Calibration Voltage Input Channel (Pga Gain = 4) Register

    Reference Manual ADuCM356 REGISTER DETAILS: ADC CIRCUIT Table 89. Bit Descriptions for ADCGAINGN2 (Continued) Bits Bit Name Settings Description Reset Access 0x4001 1.000061 (minimum positive gain adjustment). 0x4000 1.0. ADC result multiplied by 1. No gain adjustment. Default value. 0x3FFF 0.999939 (minimum negative gain adjustment).

  • Page 76: Gain Calibration Voltage Input Channel (Pga Gain = 4) Register

    Reference Manual ADuCM356 REGISTER DETAILS: ADC CIRCUIT GAIN CALIBRATION VOLTAGE INPUT CHANNEL (PGA GAIN = 4) REGISTER Address: 0x400C2278, Reset: 0x00004000, Name: ADCGAINGN4 Table 91. Bit Descriptions for ADCGAINGN4 Bits Bit Name Settings Description Reset Access [31:15] Reserved Reserved. [14:0] VALUE Gain Calibration PGA Gain 4.

  • Page 77: Gain Calibration Temperature Sensor Channel 0 Register

    Reference Manual ADuCM356 REGISTER DETAILS: ADC CIRCUIT Table 94. Bit Descriptions for ADCOFFSETTEMPSENS0 Bits Bit Name Settings Description Reset Access [31:15] Reserved Reserved. [14:0] VALUE Offset Calibration Temperature Sensor. ADC offset correction for temperature sensor channel, represented as a twos complement number. The calibration resolution is 0.25 LSBs of the ADCDAT LSB size.

  • Page 78: Maximum Slow Moving Register

    Reference Manual ADuCM356 REGISTER DETAILS: ADC CIRCUIT Table 98. Bit Descriptions for ADCMAX Bits Bit Name Settings Description Reset Access [31:16] Reserved Reserved. [15:0] MAXVAL ADC Maximum Threshold. Optional maximum ADCDAT threshold. If a value greater than ADCMAX is measured by the ADC, ADCINTSTA, Bit 5 is set to 1.
  • Page 79 Reference Manual ADuCM356 REGISTER DETAILS: ADC CIRCUIT analog.com Rev. A | 79 of 312...

  • Page 80: Key Access For Dspupdateen Register

    Reference Manual ADuCM356 REGISTER DETAILS: ADC CIRCUIT KEY ACCESS FOR DSPUPDATEEN REGISTER Address: 0x400C0434, Reset: 0x00000000, Name: MKEY Table 103. Bit Descriptions for MKEY Bits Bit Name Settings Description Reset Access [15:0] Key Access for DSPUPDATEEN Register. To access the DSPUPDATEEN register, write 0xA51F to this register first.

  • Page 81: Low-Power Potentiostat Amplifiers And Low-Power Tias

    Reference Manual ADuCM356 LOW-POWER POTENTIOSTAT AMPLIFIERS AND LOW-POWER TIAS The ADuCM356 features two low-power TIAs and two low-power Figure 15 shows the potentiostat amplifier connected to a 3-lead potentiostat amplifiers. This section details the operation of these electrochemical sensor. The potentiostat amplifier (labeled PA in components.
  • Page 82 Reference Manual ADuCM356 LOW-POWER POTENTIOSTAT AMPLIFIERS AND LOW-POWER TIAS Figure 16. Low-Power TIA, Low-Power Potentiostat, and Low-Power DAC Switches for Channel 0 analog.com Rev. A | 82 of 312...
  • Page 83 Do not use this feature more frequently or for longer than GAIN When R is large, it uses resistors from the R bank, which specified in the data sheet. See the ADuCM356 data sheet for full LOAD GAIN reduces the size of R . See the descriptions in the LPTIACON0 specifications.

  • Page 84: Low-Power Dacs

    Reference Manual ADuCM356 LOW-POWER POTENTIOSTAT AMPLIFIERS AND LOW-POWER TIAS The main 6-bit string with the 6-bit subDAC provides the VBIAS0 External R Gain Resistor with Low-Power DAC output. In 12-bit mode, the MSBs select a resistor from the TIA Amplifiers main string DAC.
  • Page 85 Reference Manual ADuCM356 LOW-POWER POTENTIOSTAT AMPLIFIERS AND LOW-POWER TIAS Figure 19. Block Diagram of Low-Power DACs unaffected. Using the high-speed TIA facilitates high bandwidth Low-Power DAC Switch Options measurements such as impedance, pulse, and cyclic voltammetry. There are a number of switch options available that allow the user To control the switches individually, use the LPDACSWx registers.
  • Page 86 Reference Manual ADuCM356 LOW-POWER POTENTIOSTAT AMPLIFIERS AND LOW-POWER TIAS 6-Bit DAC Output Voltage = 0.2 V + (LPDACDATx, If LPDACDATx, Bits[11:0] = 4095, the minimum voltage on the Bits[17:12] × 34.38 mV) 12-bit output is 2.39946 V, because LPDACDATx, Bits[11:0] = 4095 has the same effect as LPDACDATx, Bits[11:0] = 4094.
  • Page 87 For some sensor types, the DC bias on the sensor must be maintained when carrying out the impedance measurement. The ADuCM356 facilitates this measurement. To maintain the DC bias on the sen- sor, set LPDACCONx, Bit 5 = 1.

  • Page 88: Register Summary: Low-Power Tia/Potentiostat And Dac Circuits

    Reference Manual ADuCM356 REGISTER SUMMARY: LOW-POWER TIA/POTENTIOSTAT AND DAC CIRCUITS Table 107. Low-Power Potentiostat and TIA Control Register Summary Address Name Description Reset Access 0x400C20EC LPTIACON0 Low-power TIA control bits Channel 0 0x00000003 0x400C20E4 LPTIASW0 Low-power TIA switch configuration for Channel 0...

  • Page 89: Register Details: Low Power Tia/Potentiostat And Dac Circuits

    Reference Manual ADuCM356 REGISTER DETAILS: LOW POWER TIA/POTENTIOSTAT AND DAC CIRCUITS LOW-POWER TIA CONTROL BITS CHANNEL 0 REGISTER Address: 0x400C20EC, Reset: 0x00000003, Name: LPTIACON0 Table 109. Bit Descriptions for LPTIACON0 Bits Bit Name Settings Description Reset Access [31:16] Reserved Reserved.

  • Page 90: Low-Power Tia Switch Configuration For Channel 0 Register

    Reference Manual ADuCM356 REGISTER DETAILS: LOW POWER TIA/POTENTIOSTAT AND DAC CIRCUITS Table 109. Bit Descriptions for LPTIACON0 (Continued) Bits Bit Name Settings Description Reset Access 10100 100 kΩ. R gain = 100 kΩ − (R − 100 Ω). LOAD 10101 120 kΩ. R gain = 120 kΩ...

  • Page 91: Low-Power Tia Control Bits Channel 1 Register

    Reference Manual ADuCM356 REGISTER DETAILS: LOW POWER TIA/POTENTIOSTAT AND DAC CIRCUITS Table 110. Bit Descriptions for LPTIASW0 (Continued) Bits Bit Name Settings Description Reset Access 1 Close switch. SW10 SW10 Switch Control Active High. 0 Open switch. 1 Close switch.
  • Page 92 Reference Manual ADuCM356 REGISTER DETAILS: LOW POWER TIA/POTENTIOSTAT AND DAC CIRCUITS Table 111. Bit Descriptions for LPTIACON1 (Continued) Bits Bit Name Settings Description Reset Access 100 200 kΩ. 101 400 kΩ. 110 600 kΩ. 111 1 MΩ. Recommended value for best DC current measurement performance. Lowest cutoff frequency setting for low-pass filter.

  • Page 93: Low-Power Tia Switch Configuration For Channel 1 Register

    Reference Manual ADuCM356 REGISTER DETAILS: LOW POWER TIA/POTENTIOSTAT AND DAC CIRCUITS Table 111. Bit Descriptions for LPTIACON1 (Continued) Bits Bit Name Settings Description Reset Access 01 Increase amplifier output stage current to quickly charge external capacitor load. Intended for use with high current sensors like oxygen electrochemical sensor.

  • Page 94: Lpdac0 Data Out Register

    Reference Manual ADuCM356 REGISTER DETAILS: LOW POWER TIA/POTENTIOSTAT AND DAC CIRCUITS Table 112. Bit Descriptions for LPTIASW1 (Continued) Bits Bit Name Settings Description Reset Access 1 Close switch. SW5 Switch Control Active High. Close to connect external capacitor or R resistor between the RC1_0 and RC1_1 pins.

  • Page 95: Lpdac0 Control Register

    Reference Manual ADuCM356 REGISTER DETAILS: LOW POWER TIA/POTENTIOSTAT AND DAC CIRCUITS Table 114. Bit Descriptions for LPDACSW0 (Continued) Bits Bit Name Settings Description Reset Access 0 Disconnect direct connection of VBIAS0 DAC output to positive input of low-power Amplifier 0.

  • Page 96: Lpdac1 Data Out Register

    Reference Manual ADuCM356 REGISTER DETAILS: LOW POWER TIA/POTENTIOSTAT AND DAC CIRCUITS LPDAC1 DATA OUT REGISTER Address: 0x400C212C, Reset: 0x00000000, Name: LPDACDAT1 Table 116. Bit Descriptions for LPDACDAT1 Bits Bit Name Settings Description Reset Access [31:18] Reserved Reserved. [17:12] DACIN6 6-Bit Value, 1 LSB = 34.375 mV. A low-power DAC1 6-bit output data register values between 0 and 0x3F is expected to set 6-bit output voltage.

  • Page 97: Low-Power Reference Control Register

    Reference Manual ADuCM356 REGISTER DETAILS: LOW POWER TIA/POTENTIOSTAT AND DAC CIRCUITS Table 118. Bit Descriptions for LPDACCON1 (Continued) Bits Bit Name Settings Description Reset Access DACMDE Low-Power DAC1 Switch Settings. Control bit for the low-power DAC1 output switches. 0 Low-Power DAC1 switches set for normal mode.

  • Page 98: High-Speed Tia Circuits

    Reference Manual ADuCM356 HIGH-SPEED TIA CIRCUITS The high-speed TIA is intended for measuring wide bandwidth input SE1 input pin from sense electrode of Channel 1 sensor. ► signals up to 200 kHz. The output of the high-speed TIA transfers to AIN0, AIN1, AIN2, and AIN3/BUF_VREF1V8 input pins.

  • Page 99: Using De0 And De1 Inputs With The High-Speed Tia

    Reference Manual ADuCM356 HIGH-SPEED TIA CIRCUITS Table 120. Configuration of R and R of High-Speed TIA When Using DE0 and DE1 Electrodes (Continued) LOAD DE0RESCON, Bits[7:0] (DE0) and DE1RESCON, Bits[7:0] (DE1) Setting and R Value (Ω) and R Value LOAD03...

  • Page 100: External Rtia Selection

    TIA is greater than the overcurrent limit protection, the amplifier clamps the current to this limit. The current clamp typically clamps at approximately 17 mA. Refer to the ADuCM356 data sheet for full specifications. Do not use this feature more frequently or for longer than specified in the data sheet.

  • Page 101: Register Summary: High-Speed Tia Circuits

    Reference Manual ADuCM356 REGISTER SUMMARY: HIGH-SPEED TIA CIRCUITS AFECON, Bit 11 and AFECON, Bit 5 are relevant to the high-speed TIA block. See Table 52 for more details. Table 121. High-Speed TIA Circuit Register Summary Address Name Description Reset Access...

  • Page 102: Register Details: High-Speed Tia Circuits

    Reference Manual ADuCM356 REGISTER DETAILS: HIGH-SPEED TIA CIRCUITS HIGH-SPEED R CONFIGURATION REGISTER Address: 0x400C20F0, Reset: 0x0000000F, Name: HSRTIACON This register controls the high-speed TIA R , current protection diode, and feedback capacitor. Table 122. Bit Descriptions for HSRTIACON Bits Bit Name...

  • Page 103: High-Speed Tia Amplifier Configuration Register

    Reference Manual ADuCM356 REGISTER DETAILS: HIGH-SPEED TIA CIRCUITS Table 124. Bit Descriptions for DE0RESCON Bits Bit Name Settings Description Reset Access [31:8] Reserved Reserved. [7:0] DE0RCON DE0 R and R Setting. DE0 high-speed TIA resistor settings. To use this R...

  • Page 104: High-Speed Dac Circuits

    Reference Manual ADuCM356 HIGH-SPEED DAC CIRCUITS The 12-bit high-speed DAC generates an AC excitation signal couple the AC signal on top of the normal DC bias voltage of the when measuring the impedance of an external sensor. The DAC sensor. Alternatively, the high-speed DAC can be used as a normal output signal can be controlled directly by writing to a data register voltage source.

  • Page 105: Recommended Configuration In Hibernate Mode

    DAC circuits are clock gated to save power. HSDACCON, Bit 12 = 1 and HSDACCON, Bit 0 = 1. This setting ► When the ADuCM356 is in active mode but the high-speed DAC ► gives a full-scale voltage of approximately ±15.1 mV to the is not required, disable the high-speed DAC circuits to save sensor for HSDACDAT Code 0x200 to Code 0xE00.

  • Page 106: Coupling An Ac Signal From High-Speed Dac Onto The Dc Level Set By Low-Power Dac

    POWER DAC low-power TIA. The AC signal generated by the high-speed DAC The ADuCM356 contains two independent low-power potentiostat is coupled onto the DC voltage level set by the low-power DAC for channels that configure two separate electrochemical sensors. In the channel under test.
  • Page 107 Reference Manual ADuCM356 HIGH-SPEED DAC CIRCUITS Gain calibration is optional and adjusts the peak-to-peak voltage swing. The peak-to-peak voltage swing can also be adjusted by changing the minimum and maximum DAC codes. Figure 25. High-Speed DAC Transfer Function The high-speed DAC transfer function is shown in...

  • Page 108: Register Summary: High-Speed Dac Circuits

    Reference Manual ADuCM356 REGISTER SUMMARY: HIGH-SPEED DAC CIRCUITS Table 128. High-Speed DAC Control Register Summary Address Name Description Reset Access 0x400C2010 HSDACCON High-speed DAC configuration 0x0000001E 0x400C2048 HSDACDAT Direct write to DAC output control value 0x00000800 0x400C2104 DACDCBUFCON DAC DC buffer configuration...

  • Page 109: Register Details: High-Speed Dac Circuits

    Reference Manual ADuCM356 REGISTER DETAILS: HIGH-SPEED DAC CIRCUITS HIGH-SPEED DAC CONFIGURATION REGISTER Address: 0x400C2010, Reset: 0x0000001E, Name: HSDACCON Table 130. Bit Descriptions for HSDACCON Bits Bit Name Settings Description Reset Access [31:13] Reserved Reserved. INAMPGNMDE Excitation Amplifier Gain Control. Selects the gain of excitation amplifier.

  • Page 110: Dac Offset With Attenuator Enabled (Low-Power Mode) Register

    Reference Manual ADuCM356 REGISTER DETAILS: HIGH-SPEED DAC CIRCUITS DAC OFFSET WITH ATTENUATOR ENABLED (LOW-POWER MODE) REGISTER Address: 0x400C2264, Reset: 0x00000000, Name: DACOFFSETATTEN The LSB adjustment is typically 4.9 μV for HSDACCON, Bit 12 = 1 and HSDACCON, Bit 0 = 1. The LSB adjustment is typically 24.7 μV for HSDACCON, Bit 12 = 1 and HSDACCON, Bit 0 = 0.

  • Page 111: Dac Offset With Attenuator Disabled (High-Power Mode) Register

    [31:5] Reserved Reserved. DACGAINCAL DAC Gain Enable. Use the DAC gain calculated during the Analog Devices factory trim and stored in the DACGAIN register. 0 Bypass DAC gain correction. 1 Enable DAC gain correction using value in the DACGAIN register.

  • Page 112: Waveform Generator For Sinusoid Phase Offset Register

    Reference Manual ADuCM356 REGISTER DETAILS: HIGH-SPEED DAC CIRCUITS WAVEFORM GENERATOR FOR SINUSOID PHASE OFFSET REGISTER Address: 0x400C2034, Reset: 0x00000000, Name: WGPHASE Table 140. Bit Descriptions for WGPHASE Bits Bit Name Settings Description Reset Access [31:20] Reserved Reserved. [19:0] SINEOFFSET Sinusoid Phase Offset. SINOFFSET, Bits[19:0] = phase (degrees)/360 × 2 .

  • Page 113: Programmable Switches Connecting The External Sensor To The High-Speed Dac And High-Speed Tia

    PROGRAMMABLE SWITCHES CONNECTING THE EXTERNAL SENSOR TO THE HIGH-SPEED DAC AND HIGH-SPEED TIA The ADuCM356 provides flexibility for connecting external pins to pin is typically RE0 or RE1. The Px switches can be connected to the high-speed DAC excitation amplifier and to the high-speed TIA an external R via the RCAL0 pin if the PR0 switch is closed.
  • Page 114 Reference Manual ADuCM356 PROGRAMMABLE SWITCHES CONNECTING THE EXTERNAL SENSOR TO THE HIGH-SPEED DAC AND HIGH-SPEED TIA Figure 27. Switch Matrix Block Diagram, All Switches Connected to High-Speed DAC Excitation Amplifier and Inverting Input of High-Speed TIA There are two options to control the programmable switches to Nx switches are controlled via SWCON, Bits[11:8].
  • Page 115 Reference Manual ADuCM356 PROGRAMMABLE SWITCHES CONNECTING THE EXTERNAL SENSOR TO THE HIGH-SPEED DAC AND HIGH-SPEED TIA The Dx switches are controlled via the DSWFULLCON register ► bits. The Px switches are controlled via the PSWFULLCON register ► bits. The Nx switches are controlled via the NSWFULLCON register ►...

  • Page 116: Register Summary: Programmable Switches

    Reference Manual ADuCM356 REGISTER SUMMARY: PROGRAMMABLE SWITCHES The status of all the switches can be read from the switch sta- switch is open or closed. The switch status registers are DSWSTA, tus registers at any time. These statuses indicate whether each PSWSTA, NSWSTA, and TSWSTA.

  • Page 117: Register Details: Programmable Switches

    Reference Manual ADuCM356 REGISTER DETAILS: PROGRAMMABLE SWITCHES SWITCH MATRIX CONFIGURATION REGISTER Address: 0x400C200C, Reset: 0x0000FFFF, Name: SWCON Table 144. Bit Descriptions for SWCON Bits Bit Name Settings Description Reset Access [31:20] Reserved Reserved. T11CON Control of T11 Switch. 1 T11 closed.

  • Page 118: Dx Switch Matrix Full Configuration Register

    Reference Manual ADuCM356 REGISTER DETAILS: PROGRAMMABLE SWITCHES Table 144. Bit Descriptions for SWCON (Continued) Bits Bit Name Settings Description Reset Access 0100 P4 closed, others open. 0101 P5 closed, others open. 0110 P6 closed, others open. 0111 P7 closed, others open.

  • Page 119: Nx Switch Matrix Full Configuration Register

    Reference Manual ADuCM356 REGISTER DETAILS: PROGRAMMABLE SWITCHES Table 145. Bit Descriptions for DSWFULLCON (Continued) Bits Bit Name Settings Description Reset Access 0 Switch open. 1 Switch closed. Control of D2 Switch. Connects the D node of the excitation amplifier to the AIN1 pin.

  • Page 120: Px Switch Matrix Full Configuration Register

    Reference Manual ADuCM356 REGISTER DETAILS: PROGRAMMABLE SWITCHES Table 146. Bit Descriptions for NSWFULLCON (Continued) Bits Bit Name Settings Description Reset Access Control of N4 Switch. Set to close the N4 switch, clear to open. Connects the N node of the excitation amplifier to the AIN3/BUF_VREF1V8 pin.

  • Page 121: Tx Switch Matrix Full Configuration Register

    Reference Manual ADuCM356 REGISTER DETAILS: PROGRAMMABLE SWITCHES Table 147. Bit Descriptions for PSWFULLCON (Continued) Bits Bit Name Settings Description Reset Access 0 Switch open. 1 Switch closed. Control of P6 Switch. Connects the P node of the excitation amplifier to the RE1 pin.

  • Page 122: Dx Switch Matrix Status Register

    Reference Manual ADuCM356 REGISTER DETAILS: PROGRAMMABLE SWITCHES Table 148. Bit Descriptions for TSWFULLCON (Continued) Bits Bit Name Settings Description Reset Access 1 Switch closed. Control of T6 Switch. Allows connection of the R path on to the DE0 input to calibrate the R...

  • Page 123: Px Switch Matrix Status Register

    Reference Manual ADuCM356 REGISTER DETAILS: PROGRAMMABLE SWITCHES Table 149. Bit Descriptions for DSWSTA (Continued) Bits Bit Name Settings Description Reset Access 0 Switch open. 1 Switch closed. D1STA Status of DR0 Switch. 0 Switch open. 1 Switch closed. PX SWITCH MATRIX STATUS REGISTER...

  • Page 124: Nx Switch Matrix Status Register

    Reference Manual ADuCM356 REGISTER DETAILS: PROGRAMMABLE SWITCHES Table 150. Bit Descriptions for PSWSTA (Continued) Bits Bit Name Settings Description Reset Access 0 Switch open. 1 Switch closed. P3STA Status of P3 Switch. 0 Switch open. 1 Switch closed. P2STA Status of P2 Switch.

  • Page 125: Tx Switch Matrix Status Register

    Reference Manual ADuCM356 REGISTER DETAILS: PROGRAMMABLE SWITCHES Table 151. Bit Descriptions for NSWSTA (Continued) Bits Bit Name Settings Description Reset Access 0 Switch open. 1 Switch closed. N2STA Status of N2 Switch. 0 Switch open. 1 Switch closed. N1STA Status of N1 Switch.
  • Page 126 Reference Manual ADuCM356 REGISTER DETAILS: PROGRAMMABLE SWITCHES Table 152. Bit Descriptions for TSWSTA (Continued) Bits Bit Name Settings Description Reset Access 0 Switch open. 1 Switch closed. T1STA Status of T1 Switch. 0 Switch open. 1 Switch closed. analog.com Rev. A | 126 of 312...

  • Page 127: Sequencer

    Four command sequences are supported by hardware on the ADuCM356. These sequences can be stored in the SRAM to switch Write Command between different measurement procedures. Only one sequence can be executed by the sequencer at a time.

  • Page 128: Sequencer Operation

    Reference Manual ADuCM356 SEQUENCER Figure 29 shows the format of the timer command, and Figure 30 the counter can be read by the host controller at any time through shows the format of the wait command. the SEQTIMEOUT register. The timeout command starts a counter that operates independently The timeout counter is not reset when the sequencer execution is of the sequencer flow.
  • Page 129 Reference Manual ADuCM356 SEQUENCER Determine the number of commands in a sequence by reading the The data FIFO is always unidirectional. A selectable source in the SEQxINFO register, Bits[26:16]. AFE block writes data and the external microcontroller reads data from the DATAFIFORD register (see Table 220).

  • Page 130: Sequencer And Fifo Registers

    Reference Manual ADuCM356 SEQUENCER is enabled. If conflicts arise, the sequencer has the priority. If the are registers that are exceptions and can be written to freely without sequencer and the processor write at the same time, the host any conflict. The SEQCON register allows ending a sequence controller is ignored.
  • Page 131 Reference Manual ADuCM356 SEQUENCER Table 155. Bit Descriptions for SEQCON Register Bits Bit Name Settings Description Reset Access [31:16] Reserved Reserved. [15:8] SEQWRTMR Sequencer Write Commands Timer. These bits act as a clock divider affecting only the write commands, not the wait commands. This divider is useful to reduce the code size when generating arbitrary waveforms.
  • Page 132 Reference Manual ADuCM356 SEQUENCER Table 157. Bit Descriptions for SEQCRC Register (Continued) Bits Bit Name Description Reset Access [7:0] Sequencer Command CRC Value. The algorithm used is CRC-8. Sequencer Command Count Register Address: 0x400C2064, Reset: 0x00000000, Name: SEQCNT The SEQCNT register forms the command count, which is incremented by 1 each time the sequencer executes a command. This register is not key protected.
  • Page 133 Reference Manual ADuCM356 SEQUENCER Table 162. Bit Descriptions for SEQSLPLOCK Register (Continued) Bits Bit Name Settings Description Reset Access [19:0] SEQ_SLP_PW SEQTRGSLP Register Password. These bits prevent the sequencer from accidentally triggering a sleep state. 0x400C Write any value other than 0xA47E5 to lock the SEQTRGSLP register.
  • Page 134 Reference Manual ADuCM356 SEQUENCER Command Data Control Register Address: 0x400C21D8, Reset: 0x00000410, Name: CMDDATACON Table 167. Bit Descriptions for CMDDATACON Register Bits Bit Name Settings Description Reset Access [31:12] Reserved Reserved. [11:9] DATAMEMMDE Data FIFO Mode Select. 10 FIFO mode.
  • Page 135 Reference Manual ADuCM356 SEQUENCER Table 170. Bit Descriptions for SEQ1INFO Register Bits Bit Name Description Reset Access [31:27] Reserved Reserved. [26:16] SEQ1INSTNUM SEQ1 Instruction Number. [15:11] Reserved Reserved. [10:0] SEQ1STARTADDR SEQ1 Start Address. Command and Data FIFO Internal Data Count Register Address: 0x400C2200, Reset: 0x00000000, Name: FIFOCNTSTA Table 171.

  • Page 136: Afe Interrupts

    Reference Manual ADuCM356 AFE INTERRUPTS There are interrupt options available on the ADuCM356 analog DioIenPin(pADI_GPIO2, PIN1, 1); /* Enable front end that can be configured to toggle the internal GPIO pin P2.1 input path. */ on the digital die. The GPIO pin is connected internally and is not bonded out of the LGA package.

  • Page 137: Interrupt Registers

    Reference Manual ADuCM356 AFE INTERRUPTS INTERRUPT REGISTERS Table 174. Interrupt Registers Summary Address Name Description Reset Access 0x400C3000 INTCPOL Interrupt polarity register 0x00000000 0x400C3004 INTCCLR Interrupt clear register 0x00000000 0x400C3008 INTCSEL0 Interrupt controller select register 0x00002000 0x400C300C INTCSEL1 Interrupt controller select register...
  • Page 138 Reference Manual ADuCM356 AFE INTERRUPTS Table 176. Bit Descriptions for INTCCLR Register (Continued) Bits Bit Name Description Reset Access INTCLR6 ADC Delta Fail IRQ. Write 1 to clear. INTCLR5 ADC Maximum Fail IRQ. Write 1 to clear. INTCLR4 ADC Minimum Fail IRQ. Write 1 to clear.
  • Page 139 Reference Manual ADuCM356 AFE INTERRUPTS Table 177. Bit Descriptions for INTCSEL0 and INTCSEL1 Registers (Continued) Bits Bit Name Settings Description Reset Access 1 Interrupt enabled. Reserved Reserved. INTSEL13 Bootloader Done IRQ Enable. 0 Interrupt disabled. 1 Interrupt enabled. INTSEL12 Custom Interrupt 3 Enable.
  • Page 140 Reference Manual ADuCM356 AFE INTERRUPTS Table 178. Bit Descriptions for INTCFLAG0 and INTCFLAG1 Registers Bits Bit Name Settings Description Reset Access FLAG31 Attempt to Break IRQ Status. This bit is set if a Sequence B request arrives when Sequence A is running, indicating that Sequence B is ignored.
  • Page 141 Reference Manual ADuCM356 AFE INTERRUPTS Table 178. Bit Descriptions for INTCFLAG0 and INTCFLAG1 Registers (Continued) Bits Bit Name Settings Description Reset Access 0 Interrupt not asserted. 1 Interrupt asserted. Reserved Reserved. FLAG7 Mean IRQ Status. 0 Interrupt not asserted. 1 Interrupt asserted.
  • Page 142 Reference Manual ADuCM356 AFE INTERRUPTS Table 179. Bit Descriptions for AFEGENINTSTA Register (Continued) Bits Bit Name Description Reset Access CUSTOMINT0 General-Purpose Custom Interrupt 0. Set this bit manually using the sequencer program. Write 1 to this bit to trigger R/W1C an interrupt.

  • Page 143: Sleep And Wake-Up Timer

    SLEEP AND WAKE-UP TIMER FEATURES period (SEQxSLEEPx) and a defined active period (SEQxWUPx). The ADuCM356 integrates a 20-bit sleep and wake-up timer. The timer is clocked from the internal 32 kHz oscillator clock The sleep and wake-up timer provides automated control of the source.

  • Page 144: Sleep And Wake-Up Timer Registers

    TMRCON register, Bit 0 = 1. If the AFE LOCK register to 0xA47E5 to enable the sequencer to trigger PWRMOD register, Bit 3 = 1, the ADuCM356 returns to sleep mode sleep. at the end of the last sequence.
  • Page 145 Reference Manual ADuCM356 SLEEP AND WAKE-UP TIMER Table 181. Bit Descriptions for CON Register (Continued) Bits Bit Name Settings Description Reset Access [5:4] RESERVED Reserved. [3:1] ENDSEQ End Sequence. These bits select one of the SEQORDER bits to end the timing sequence.
  • Page 146 Reference Manual ADuCM356 SLEEP AND WAKE-UP TIMER Table 182. Bit Descriptions for SEQORDER Register (Continued) Bits Bit Name Settings Description Reset Access 01 Fills in SEQ1. 10 Fills in SEQ2. 11 Fills in SEQ3. [3:2] SEQB Sequence B Configuration. These bits select SEQ0, SEQ1, SEQ2, or SEQ3 for Timer Sequence B.
  • Page 147 Reference Manual ADuCM356 SLEEP AND WAKE-UP TIMER Address: 0x400C0820, Reset: 0xFFFF, Name: SEQ1SLEEPL Address: 0x400C0830, Reset: 0xFFFF, Name: SEQ2SLEEPL Address: 0x400C0840, Reset: 0xFFFF, Name: SEQ3SLEEPL The SEQxSLEEPL registers define the device active time for SEQ0 to SEQ3. The counter is 20 bits. These registers set the 16 LSBs.

  • Page 148: Use Case Configurations

    To maintain a bias voltage to an electrochemical sensor, the electrochemical sensors. This section gives suggested setup details recommended analog die configuration setting for the low-power for the main use cases of the ADuCM356 with an electrochemical potentiostat amplifier and low-power TIA is LPTIASWx = 0x302C. sensor.

  • Page 149: Measuring A Dc Current Output

    Reference Manual ADuCM356 USE CASE CONFIGURATIONS Figure 37. Recommended Switch Settings to Minimize Leakage in Hibernate Mode of Unused AFE Circuits trode and reference electrode, the V and V DAC outputs MEASURING A DC CURRENT OUTPUT BIAS ZERO must be set to the same voltage. Likewise, LPDACDAT0 = 0x1A680 When measuring a DC current output, the ADC is powered on and sets both VBIAS0 and VZERO0 outputs to approximately 1.1 V.
  • Page 150 TIA output filter. Using the provided software libraries, the following function call selects LPTIA0 as the ADC input: The ADuCM356 ADC provides optional digital postprocessing and filtering that can improve measurement accuracy of the sensor AfeAdcChan(MUXSELP_LPTIA0_LPF, measurement.

  • Page 151: Pulse Test (Chronoamperometry)

    Reference Manual ADuCM356 USE CASE CONFIGURATIONS Figure 38. Switches for Low-Power Potentiostat Amplifier and Low-Power TIA to Measure DC Current from SE0 Node Using Low-Power TIA (3-Wire Electrochemical Sensor Configuration) or SE1 pin is routed to the high-speed TIA instead of the low-power PULSE TEST (CHRONOAMPEROMETRY) TIA.

  • Page 152: Cyclic Voltammetry

    Reference Manual ADuCM356 USE CASE CONFIGURATIONS setting Exiting Cyclic Voltammetry Mode section for recommendations to BITM_HSTIA_CTIA_1PF, // inter► decrease the settling time of the sensor when exiting pulse testing. nal load of 1pF CYCLIC VOLTAMMETRY // pro► tection diodes disconnected...
  • Page 153 Reference Manual ADuCM356 USE CASE CONFIGURATIONS Figure 39. Switches for Low-Power Potentiostat, Low-Power TIA, and Switch Matrix to Perform Cyclic Voltammetry or Pulse Test on SE0 Node Using High-Speed analog.com Rev. A | 153 of 312...

  • Page 154: Ac Impedance Measurement While Maintaining Dc Bias To The Sensor

    Reference Manual ADuCM356 USE CASE CONFIGURATIONS Figure 40. Signal Path for Low-Power Potentiostat, Low-Power TIA, and Switch Matrix to Perform Cyclic Voltammetry or Pulse Test on SE0 Node Using High-Speed for normal switch operation around the low-power DACs. Set up...
  • Page 155 DACOFFSET, DACOFFSETATTEN, DACOFFSETHP, electrode of a 3-electrode electrochemical sensor. and DACOFFSETATTENHP. The relevant register depends on the excitation amplifier gain setting and whether the device is in Step 1: Initialize ADuCM356 for Impedance low or high-power mode. See Table 127.
  • Page 156 Reference Manual ADuCM356 USE CASE CONFIGURATIONS the electrochemical sensor reference electrode and the high-speed Step 2: Measure R and External Sensor LOAD02 TIA input. The reference electrode + R is included in this LOAD02 SENSOR AC excitation loop. At this point, the high-speed TIA output is The electrochemical sensor remains biased during this step, but the measured via the ADC signal chain.
  • Page 157 Reference Manual ADuCM356 USE CASE CONFIGURATIONS via the high-speed TIA. The ADC signal chain and DFT are used to OAD,SWID_T5_SE0RLOAD|SWID_T9); // Connect Excitation Amplifier D to the WE calculate the impedance of the R resistor. LOAD02 Electrode Configure the Tx, Dx, Nx, and Px switches appropriately, as descri-...
  • Page 158 Reference Manual ADuCM356 USE CASE CONFIGURATIONS Figure 43. R Measurement The R measurement is used to calibrate the R SENSOR LOAD measurement in Step 3 by using ratiometric measurements. As shown in Figure 43, the electrochemical sensor is biased via the low-power potentiostat and low-power TIA amplifiers for Step 4.
  • Page 159 Reference Manual ADuCM356 USE CASE CONFIGURATIONS − Z − Therefore, based on Step 2 through Step 4, Step 5: Calculate the Impedance of RE + RLOAD02 RLOAD02 I s RE + RLOAD02 I s RLOAD02 Electrochemical Sensor Sensing Electrode =I s ×...

  • Page 160: Dma Controller

    Memory to peripheral. ► Peripheral to memory. ► The ADuCM356 provides dedicated and independent DMA chan- nels. There are two programmable priority levels for each DMA DMA OVERVIEW channel. Each priority level arbitrates using a fixed priority that The DMA controller has 20 channels in total. The 20 channels are is determined by the DMA channel number.

  • Page 161: Dma Operating Modes

    Reference Manual ADuCM356 DMA CONTROLLER either the primary or the alternate data structure. For more complex DMA OPERATING MODES data transfer modes, such as ping pong or scatter gather, the DMA The DMA controller has two buses, one connected to the system controller uses both the primary and alternate data structures.

  • Page 162: Source Data End Pointer

    Reference Manual ADuCM356 DMA CONTROLLER until the DMA_DONE interrupt is received does not guarantee pADI_DMA->CFG = 1; Enable DMA controller expected behavior. It is recommended that the user not update the pADI_DMA->PDBPTR = uiBasPtr; descriptor before receiving DMA_DONE. SOURCE DATA END POINTER...
  • Page 163 Reference Manual ADuCM356 DMA CONTROLLER Table 193. CHNL_CFG Control Data Configuration (Continued) Source Bit(s) Name Data Width Setting Description 01 Source address increment is half word. 10 Source address increment is word. 11 No increment. Address remains set to the value contained in the SRC_END_PTR memory location.

  • Page 164: Dma Priority

    Reference Manual ADuCM356 DMA CONTROLLER Table 193. CHNL_CFG Control Data Configuration (Continued) Source Bit(s) Name Data Width Setting Description 100 Memory scatter gather primary. 101 Memory scatter gather alternate. 110 Peripheral scatter gather primary. 111 Peripheral scatter gather alternate. During the DMA transfer process, if any error occurs during the...
  • Page 165 Reference Manual ADuCM356 DMA CONTROLLER the completion of primary or alternate descriptor tasks. This final Software Ping Pong DMA Transfer descriptor must use an autorequest transfer type. This mode is (CHNL_CFG, Bits[2:0] = 011) shown in Figure In this mode, if the DMA request comes from the software, a request is generated automatically after each arbitration cycle until Figure 44.
  • Page 166 Reference Manual ADuCM356 DMA CONTROLLER Table 194. CHNL_CFG for Primary Data Structure in Memory Scatter Gather Mode, CHNL_CFG, Bits[2:0] = 100 Bit(s) Name Description [31:30] DST_INC Set to 10, configures the controller to use word increments for the address. [29:28] Reserved Undefined.

  • Page 167: Dma Interrupts And Exceptions

    Reference Manual ADuCM356 DMA CONTROLLER DMA cycle using the alternate data structure without rearbitrating. Table 195 lists the fields of the CHNL_CFG memory location for the The controller continues to alternate between using the primary and primary data structure, which must be programmed with constant alternate data structures until the processor configures the alternate values for the peripheral scatter gather mode.
  • Page 168 Reference Manual ADuCM356 DMA CONTROLLER count. The user can check the N count to determine how many data values written into the source data end pointer (SRC_END_PTR) transfers occurred before the bus error. and destination data end pointer (DST_END_PTR) are still used as the addresses for the last transfer as part of the DMA cycle.

  • Page 169: Endian Operation

    Reference Manual ADuCM356 DMA CONTROLLER Whenever a channel is disabled, based on the current state of the Aborting DMA Transfers DMA controller, the channel does one of the following: It is possible to abort a DMA transfer that is in progress by writing...

  • Page 170: Register Summary: Dma

    Reference Manual ADuCM356 REGISTER SUMMARY: DMA Table 196. DMA Register Summary Address Name Description Reset Access 0x40010000 STAT Status 0x00180000 0x40010004 Configuration 0x00000000 0x40010008 PDBPTR Channel primary control data base pointer 0x00000000 0x4001000C ADBPTR Channel alternate control data base pointer...

  • Page 171: Register Details: Dma

    Reference Manual ADuCM356 REGISTER DETAILS: DMA STATUS REGISTER Address: 0x40010000, Reset: 0x00180000, Name: STAT Table 197. Bit Descriptions for STAT Bits Bit Name Settings Description Reset Access [31:21] Reserved Reserved. 0x000 [20:16] CHANM1 Number of Available DMA Channels Minus 1. With 24 channels available, the register reads back 0x17.

  • Page 172: Channel Request Mask Set Register

    Reference Manual ADuCM356 REGISTER DETAILS: DMA Table 201. Bit Descriptions for SWREQ Bits Bit Name Settings Description Reset Access [31:24] Reserved Reserved. 0x00 [23:0] CHAN Generate Software Request. Set the appropriate bit to generate a software DMA request on the 0x000000 corresponding DMA channel.

  • Page 173: Channel Enable Clear Register

    Reference Manual ADuCM356 REGISTER DETAILS: DMA CHANNEL ENABLE CLEAR REGISTER Address: 0x4001002C, Reset: 0x00000000, Name: EN_CLR Table 205. Bit Descriptions for EN_CLR Bits Bit Name Settings Description Reset Access [31:24] Reserved Reserved. 0x00 [23:0] CHAN Disable DMA Channels. This register allows the disabling of DMA channels. This register is write 0x000000 only.

  • Page 174: Channel Priority Clear Register

    Reference Manual ADuCM356 REGISTER DETAILS: DMA Table 208. Bit Descriptions for PRI_SET Bits Bit Name Settings Description Reset Access [31:24] Reserved Reserved. 0x00 [23:0] CHAN Configure Channel Priority. This register enables the user to configure a DMA channel to use the 0x000000 high priority level.
  • Page 175 Reference Manual ADuCM356 REGISTER DETAILS: DMA Table 211. Bit Descriptions for ERRCHNL_CLR (Continued) Bits Bit Name Settings Description Reset Access 1 When read as 1, a bus error control is pending. When written as 1, bit is cleared. analog.com Rev. A | 175 of 312...

  • Page 176: Per Channel Invalid Descriptor Clear Register

    Reference Manual ADuCM356 REGISTER DETAILS: DMA PER CHANNEL INVALID DESCRIPTOR CLEAR REGISTER Address: 0x40010050, Reset: 0x00000000, Name: INVALIDDESC_CLR Table 212. Bit Descriptions for INVALIDDESC_CLR Bits Bit Name Settings Description Reset Access [31:24] Reserved Reserved. 0x00 [23:0] CHAN Per Channel Invalid Descriptor Status and Per Channel Invalid Descriptor Status Clear. This...

  • Page 177: Channel Source Address Decrement Enable Clear Register

    Reference Manual ADuCM356 REGISTER DETAILS: DMA Table 215. Bit Descriptions for SRCADDR_SET (Continued) Bits Bit Name Settings Description Reset Access 0 When read as 0, Channel C source address decrement is disabled. When written as 0, no effect. Use the SRCADDR_CLR register to disable source address decrement on Channel C.

  • Page 178: Fifo Configuration Register

    Reference Manual ADuCM356 REGISTER DETAILS: DMA FIFO CONFIGURATION REGISTER Address: 0x400C2008, Reset: 0x00001010, Name: FIFOCON Table 219. Bit Descriptions for FIFOCON Bits Bit Name Settings Description Reset Access [31:16] Reserved Reserved. [15:13] DATAFIFOSRCSEL Selects the Source for the Data FIFO.

  • Page 179: Flash Controller

    ► Write. Provided by a keyhole mechanism through memory map- ► The ADuCM356 processor includes 256 kB of embedded flash ped registers. memory available for access through the flash controller. The em- Mass erase. Clears all user data and program code.

  • Page 180: Flash Memory Structure

    User code can perform a mass erase com- generally stores a bootloader (kernel), several trim and calibration mand on the ADuCM356 without affecting the content of information values, and other device specific metadata. All but the top 128 space.

  • Page 181: Flash Access

    Reference Manual ADuCM356 FLASH CONTROLLER Figure 52. ADuCM356 Flash Memory Structure, Top of Page 128, Address 0x3F800 to 0x3FFFF When writing to these locations, the user must always write FLASH ACCESS 0xFFFFFFFF to the reserved locations. If the user intends to write Flash memory can be read, written, and erased by user code.

  • Page 182: Erasing Flash

    Reference Manual ADuCM356 FLASH CONTROLLER more than twice per erasure can damage the nonvolatile memory ERASING FLASH or reduce its useful life. If multiple writes per location are required, The flash controller provides page level granularity when erasing disable ECC for some region of flash and target that region for user space through the erase page command.

  • Page 183: Dma Writes

    Reference Manual ADuCM356 FLASH CONTROLLER The following list outlines the procedure for performing multiple During a burst write, the flash controller overlaps the write opera- writes with the potential to burst within a row: tions and, therefore, any reported write failures (such as access denied due to write protection) may reflect the status of either of the 1.
  • Page 184 Reference Manual ADuCM356 FLASH CONTROLLER the device to Analog Devices for failure analysis. If the information from its reset value. The BLANKCHECK command is always per- space integrity check does not pass, the flash controller enters mitted to execute, but only passes if all user space is already in an a special purpose debugging mode.

  • Page 185: Key Register

    Reference Manual ADuCM356 FLASH CONTROLLER write the same values to the WRPROT register. When writing the the 32‑bit signature word) must be written all at once. Otherwise, WRPROT metadata, consider including write protection of the least the ECC byte is corrupted by the second write. If using the flash...
  • Page 186 Reference Manual ADuCM356 FLASH CONTROLLER User Key This key serves to prevent accidental access to some flash features and addresses. The key value is 0x676C7565. This key must be entered to run protected user commands (erase page, sign, mass erase, and abort) or to enable write access to the UCFG register. When entered, the key remains valid until an incorrect value is written to the key register, or a command is written to the CMD register.

  • Page 187: Clock And Timings

    STAT, Bits[5:4] = 11 to match expected user code checks for status register values. The flash memory used by the ADuCM356 processor supports the following power optimizing features. Power-Down Mode Support...
  • Page 188 Reference Manual ADuCM356 FLASH CONTROLLER Flash Programming Model This list provides an example sequence to execute the page erase command using the flash controller. The same sequence can be used for other commands with some modifications: 1. Program the PAGE_ADDR0 or PAGE_ADDR1 register with the address of the page that must be erased.

  • Page 189: Register Summary: Flash Cache Controller

    ABORT_EN_LO IRQ abort enable (lower bits) 0x00000000 0x40018040 ABORT_EN_HI IRQ abort enable (upper bits) 0x00000000 0x40018044 ECC_CFG ECC configuration 0x00000002 0x40018048 ECC_ADDR ECC status (address) 0x00000000 0x40018050 ADI_POR_SEC Analog Devices flash security 0x00000000 analog.com Rev. A | 189 of 312...

  • Page 190: Register Details: Flash Cache Controller (Flcc)

    Reference Manual ADuCM356 REGISTER DETAILS: FLASH CACHE CONTROLLER (FLCC) STATUS REGISTER Address: 0x40018000, Reset: 0x00000000, Name: STAT This register provides information on current command states, error detection, and correction. Table 224. Bit Descriptions for STAT Bits Bit Name Settings Description...
  • Page 191 Reference Manual ADuCM356 REGISTER DETAILS: FLASH CACHE CONTROLLER (FLCC) Table 224. Bit Descriptions for STAT (Continued) Bits Bit Name Settings Description Reset Access subsequent AHB read access incurred the alternate ECC error event. By default, 1-bit ECC corrections are reported as IRQs and 2-bit ECC errors are reported as bus faults. It is not recommended to report both types as IRQs, because the status bits become ambiguous when trying to diagnose which fault came first.

  • Page 192: Interrupt Enable Register

    Reference Manual ADuCM356 REGISTER DETAILS: FLASH CACHE CONTROLLER (FLCC) Table 224. Bit Descriptions for STAT (Continued) Bits Bit Name Settings Description Reset Access and this bit asserting. Watch the CMDCOMP bit rather than this bit when polling for command completion.

  • Page 193: Write Address Register

    Reference Manual ADuCM356 REGISTER DETAILS: FLASH CACHE CONTROLLER (FLCC) Table 226. Bit Descriptions for CMD (Continued) Bits Bit Name Settings Description Reset Access flash. It is always advisable to erase the affected region and reprogram it. Depending on how far along the flash controller is in the process of performing a command, an abort is not always possible.
  • Page 194 Reference Manual ADuCM356 REGISTER DETAILS: FLASH CACHE CONTROLLER (FLCC) Table 228. Bit Descriptions for KH_DATA0 Bits Bit Name Settings Description Reset Access [31:0] VALUE Lower Half of 64-Bit Dual-Word Data to Be Written on a Write Command. 0xFFFFFFFF analog.com Rev. A | 194 of 312...

  • Page 195: Write Upper Data Register

    Reference Manual ADuCM356 REGISTER DETAILS: FLASH CACHE CONTROLLER (FLCC) WRITE UPPER DATA REGISTER Address: 0x40018014, Reset: 0xFFFFFFFF, Name: KH_DATA1 This register contains the upper half of 64-bit dual-word data to be written to flash. Table 229. Bit Descriptions for KH_DATA1...

  • Page 196: Write Abort Address Register

    All write protection is cleared on a POR, but the Analog Devices bootloader reasserts write protection (as defined by the WRPROT word) in user space before enabling user access to the flash array. Removing write protection can only be performed by an erase page command of the most significant page in user space (provided that page is not currently protected) or by a mass erase command.

  • Page 197: User Configuration Register

    Reference Manual ADuCM356 REGISTER DETAILS: FLASH CACHE CONTROLLER (FLCC) USER CONFIGURATION REGISTER Address: 0x40018030, Reset: 0x00000000, Name: UCFG User key is required. Write to this register to enable user control of DMA and autoincrement features. When user code has finished accessing this register, write arbitrary data to the key register to reassert protection.
  • Page 198 Reference Manual ADuCM356 REGISTER DETAILS: FLASH CACHE CONTROLLER (FLCC) Table 239. Bit Descriptions for ECC_CFG (Continued) Bits Bit Name Settings Description Reset Access INFOEN Information Space ECC Enable Bit. ECC is enabled by default for information space. Clearing this bit disables ECC in information space.

  • Page 199: Ecc Status (Address) Register

    Reserved Reserved. [18:0] VALUE Address for Which ECC Error Is Detected. ANALOG DEVICES FLASH SECURITY REGISTER Address: 0x40018050, Reset: 0x00000000, Name: ADI_POR_SEC This register resets only after a POR or an external reset. Table 241. Bit Descriptions for ADI_POR_SEC Bits...

  • Page 200: Sram

    SRAM FEATURES ► SRAM is reserved for cache data. Those 4 kB of cache data are The SRAM used by the ADuCM356 processor supports the follow- not retained in hibernate mode. ing features: Parity bit error detection (optional) is available on all SRAM ►...

  • Page 201: Sram Retention In Hibernate Mode

    Reference Manual ADuCM356 SRAM If SRAM_CTL, Bit 31 is 0 and cache is disabled, the 64 kB of SRAM INITIALIZATION SRAM is mapped as data SRAM. The memory is arranged in two If parity check is enabled, SRAM contents must be initialized sections.

  • Page 202: Cache

    Reference Manual ADuCM356 CACHE INITIALIZATION IN CACHE AND INSTRUCTION SRAM Enabling the cache provides a significant performance increase for applications executing from flash. Cache memory coexists with SRAM. When cache is enabled, part of the SRAM is allocated to the cache memory, and as such, cache memory cannot be used for other purposes.

  • Page 203: Register Summary: Cache (Flcc)

    Reference Manual ADuCM356 REGISTER SUMMARY: CACHE (FLCC) Table 242. FLCC Register Summary Address Name Description Reset Access 0x40018058 STAT Cache status 0x00000000 0x4001805C SETUP Cache setup 0x00000000 0x40018060 Cache key 0x00000000 analog.com Rev. A | 203 of 312...

  • Page 204: Register Details: Cache (Flcc)

    Reference Manual ADuCM356 REGISTER DETAILS: CACHE (FLCC) CACHE STATUS REGISTER Address: 0x40018058, Reset: 0x00000000, Name: STAT Table 243. Bit Descriptions for STAT Bits Bit Name Settings Description Reset Access [31:1] Reserved Reserved. 0x0000000 ICEN Instruction Cache Enable. 0 Disabled. All AHB accesses take place via flash memory.

  • Page 205: Silicon Identification

    Reference Manual ADuCM356 SILICON IDENTIFICATION The digital and analog dice of the ADuCM356 contain a chip ID automated test equipment (ATE) test program, kernel revisions, and and hardware revision register that can be read by software to unique chip ID number can be read from the read only locations allow users to determine the current revision of the silicon.

  • Page 206: Register Summary: System (Digital Die)

    ADuCM356 REGISTER SUMMARY: SYSTEM (DIGITAL DIE) Table 247. System Register Summary Address Name Description Reset Access 0x40002020 ADIID Analog Devices identification (digital die) 0x4144 0x40002024 CHIPID Chip identifier (digital die) 0x0284 0x40002040 SWDEN Serial wire debug enable 0x6E65 Table 248. AFE Control Register Summary...

  • Page 207: Register Details: System (Digital Die)

    Reset Access [15:0] VALUE Analog Devices Identification. Reads a fixed value of 0x4144 to indicate to debuggers that they are 0x4144 connected to an Analog Devices implemented Cortex-based device. CHIP IDENTIFIER (DIGITAL DIE) REGISTER Address: 0x40002024, Reset: 0x0284, Name: CHIPID Chip identification for the digital die.

  • Page 208: 16-Bit Scratch Register To Test Interdie Communications Register

    Reference Manual ADuCM356 REGISTER DETAILS: SYSTEM (DIGITAL DIE) 16-BIT SCRATCH REGISTER TO TEST INTERDIE COMMUNICATIONS REGISTER Address: 0x400C0428, Reset: 0xAA55, Name: DIE2DIESTA Table 254. Bit Descriptions for DIE2DIESTA Bits Bit Name Settings Description Reset Access [15:0] User Programmable Scratch Register. The user can use this register to prove interdie communications.

  • Page 209: Digital Inputs And Outputs

    GPIOs configured as input or open circuit The GPIOs are grouped into three ports, Port 0, Port 1, and Port is 10 nA per GPIO. When the ADuCM356 enters a power saving 2. Each GPIO can be configured as an input, output, or fully open mode, the GPIO pins retain their states.

  • Page 210: Interrupts

    Reference Manual ADuCM356 DIGITAL INPUTS AND OUTPUTS Input/Output Pull-Up Enable (GPxPE) Interrupt B Enable In input mode, the GPxPE registers enable and disable internal Each GPIO port has a corresponding Interrupt Enable B (GPxIENB) pull-up resistors. All Port 0, Port 1, and Port 2 pins have internal register that is enabled or masked for each pin in the port.

  • Page 211: Digital Die Port Mux

    Reference Manual ADuCM356 DIGITAL INPUTS AND OUTPUTS The following is example code for the GPIO pin interrupt handler The following is example code to set P0.3/SPI0_CS as an output. routine: Write to GP0OUT, GP0SET, GP0CLR, and GP0TGL to set the level on P0.3/SPI0_CS:...

  • Page 212: Register Summary: Digital Inputs And Outputs

    Reference Manual ADuCM356 REGISTER SUMMARY: DIGITAL INPUTS AND OUTPUTS Table 257. Digital Die GPIO Register Summary Address Name Description Reset Access 0x40020000 GP0CON GPIO Port 0 configuration 0x00000000 0x40020004 GP0OEN GPIO Port 0 output enable 0x0000 0x40020008 GP0PE GPIO Port 0 input/output pull-up enable...
  • Page 213 Reference Manual ADuCM356 REGISTER SUMMARY: DIGITAL INPUTS AND OUTPUTS Table 258. AFE Die GPIO Register Summary (Continued) Address Name Description Reset Access 0x400C0090 AFE GPIO port registered data input 0x400C0094 AFE GPIO port data output 0x400C0098 AFE GPIO port data output set...

  • Page 214: Register Details: Digital Inputs And Outputs

    Reference Manual ADuCM356 REGISTER DETAILS: DIGITAL INPUTS AND OUTPUTS Not all bits are accessible to the user on every port. Inaccessible bits are reserved. See Table 255 for more details on the accessible bits. GPIO PORT CONFIGURATION REGISTERS Address: 0x40020000, Reset: 0x00000000, Name: GP0CON...

  • Page 215: Gpio Port Input Path Enable Registers

    Reference Manual ADuCM356 REGISTER DETAILS: DIGITAL INPUTS AND OUTPUTS Table 261. Bit Descriptions for GP0PE, GP1PE, GP2PE Bits Bit Name Settings Description Access [15:0] Pin Pull-Up Enable in Input and Output Mode. 0 Disable the pull-up resistor on the corresponding GPIO.
  • Page 216 Reference Manual ADuCM356 REGISTER DETAILS: DIGITAL INPUTS AND OUTPUTS Table 265. Bit Descriptions for GP0SET, GP1SET, GP2SET (Continued) Bits Bit Name Settings Description Access 0 Clearing this bit has no effect. 1 Set by user code to drive the corresponding GPIO high.

  • Page 217: Gpio Port Data Output Clear Registers

    Reference Manual ADuCM356 REGISTER DETAILS: DIGITAL INPUTS AND OUTPUTS GPIO PORT DATA OUTPUT CLEAR REGISTERS Address: 0x4002001C, Reset: 0x0000, Name: GP0CLR Address: 0x4002005C, Reset: 0x0000, Name: GP1CLR Address: 0x4002009C, Reset: 0x0000, Name: GP2CLR Table 266. Bit Descriptions for GP0CLR, GP1CLR, GP2CLR...

  • Page 218: Gpio Port Interrupt B Enable Registers

    Reference Manual ADuCM356 REGISTER DETAILS: DIGITAL INPUTS AND OUTPUTS GPIO PORT INTERRUPT B ENABLE REGISTERS Address: 0x4002002C, Reset: 0x0000, Name: GP0IENB Address: 0x4002006C, Reset: 0x0000, Name: GP1IENB Address: 0x400200AC, Reset: 0x0000, Name: GP2IENB Table 270. Bit Descriptions for GP0IENB, GP1IENB, GP2IENB...

  • Page 219: Afe Gpio Port Output Enable Register

    Reference Manual ADuCM356 REGISTER DETAILS: DIGITAL INPUTS AND OUTPUTS AFE GPIO PORT OUTPUT ENABLE REGISTER Address: 0x400C0084, Reset: 0x0, Name: OEN Table 274. Bit Descriptions for OEN Bits Bit Name Settings Description Reset Access [15:3] Reserved Reserved. 0x0000 OEN1 Output Enable for AFE Die Clock to Digital Die. The AFE die Pad P2.2 is internally connected to the digital die internal Pad P1.10.

  • Page 220: Afe Gpio Port Data Output Set Register

    Reference Manual ADuCM356 REGISTER DETAILS: DIGITAL INPUTS AND OUTPUTS AFE GPIO PORT DATA OUTPUT SET REGISTER Address: 0x400C0098, Reset: 0x0, Name: SET Table 279. Bit Descriptions for SET Bits Bit Name Settings Description Reset Access [15:2] Reserved Reserved. 0x0000 [1:0] Set Output High for the AFE Die Port Pins (GPIOx/PWMx).

  • Page 221: I 2 C Serial Interface

    The ID0 register, ID1 register, ID2 register, and ID3 register contain The following steps are required to run the I C peripheral: the target device IDs. The ADuCM356 compares the four IDx registers to the address byte. To be correctly addressed, the seven 1. Enable PCLK to the I...
  • Page 222 Reference Manual ADuCM356 C SERIAL INTERFACE register contains the remaining eight bits of the 10-bit address. The the initiator must first send a 10-bit address with the R/W bit ID2 register and ID3 register can still be programmed with 7-bit cleared.

  • Page 223: I 2 C Operating Modes

    Reference Manual ADuCM356 C SERIAL INTERFACE In initiator mode, the steps are as follows: Register ID1, Register ID2, or Register ID3. If the device address is recognized, the device participates in the target transfer sequence. 1. Clear MCTL, Bit 0 to 0 and disable the I C initiator.
  • Page 224 Reference Manual ADuCM356 C SERIAL INTERFACE The transmit FIFO is empty when a valid read request is active 0x4. The general call interrupt status bit is asserted, and the ► ► for the initiator or target. general call ID bits (SSTAT, Bits[9:8]) are 0x2.
  • Page 225 C Pins when ADuCM356 is Unpowered When the ADuCM356 is not powered up, do not apply logic high signals to any digital pins. The maximum voltage that can be applied to a digital input pin at any time is DVDD + 0.3 V. If this limit is exceeded, the ESD protection diodes start to conduct to ground.

  • Page 226: Register Summary: I 2 C

    Reference Manual ADuCM356 REGISTER SUMMARY: I Table 282. I C Register Summary Address Name Description Reset Access 0x40003000 MCTL Initiator control 0x0000 0x40003004 MSTAT Initiator status 0x6000 0x40003008 Initiator receive data 0x0000 0x4000300C Initiator transmit data 0x0000 0x40003010 MRXCNT Initiator receive data count...

  • Page 227: Register Details: I 2 C

    Reference Manual ADuCM356 REGISTER DETAILS: I INITIATOR CONTROL REGISTER Address: 0x40003000, Reset: 0x0000, Name: MCTL Table 283. Bit Descriptions for MCTL Bits Bit Name Settings Description Reset Access [15:12] Reserved Reserved. MTXDMA Enable Initiator Transmit DMA Request. 0 Disable DMA mode.

  • Page 228: Initiator Receive Data Register

    Reference Manual ADuCM356 REGISTER DETAILS: I Table 284. Bit Descriptions for MSTAT (Continued) Bits Bit Name Settings Description Reset Access MTXUNDR Initiator Transmit Underflow. Asserts when the I C initiator ends the transaction due to the transmit FIFO being empty. This bit is asserted only when MCTL, Bit 5 is set.

  • Page 229: Initiator Receive Data Count Register

    Reference Manual ADuCM356 REGISTER DETAILS: I Table 286. Bit Descriptions for MTX (Continued) Bits Bit Name Settings Description Reset Access [7:0] VALUE Initiator Transmit. For test and debug purposes, when read, this register returns the byte that is currently being transmitted by the initiator. A byte written to the transmit register can be read back later when that byte is being transmitted on the line.

  • Page 230: Serial Clock Period Divisor Register

    Reference Manual ADuCM356 REGISTER DETAILS: I SERIAL CLOCK PERIOD DIVISOR REGISTER Address: 0x40003024, Reset: 0x1F1F, Name: DIV Table 291. Bit Descriptions for DIV Bits Bit Name Settings Description Reset Access [15:8] HIGH Serial Clock High Time. This register controls the clock high time. The PCLK drives the timer. To derive the 0x1F required high time, calculate: High = (REQD_HIGH_TIME/PCLK_PERIOD) –...

  • Page 231: Target I 2 C Status, Error, And Irq Register

    Reference Manual ADuCM356 REGISTER DETAILS: I Table 292. Bit Descriptions for SCTL (Continued) Bits Bit Name Settings Description Reset Access supported by the target and is stored in ID0 and ID1, where ID0 contains the first byte of the address and the upper 5 bits must be programmed to 11110.

  • Page 232: Target Receive Register

    Reference Manual ADuCM356 REGISTER DETAILS: I Table 293. Bit Descriptions for SSTAT (Continued) Bits Bit Name Settings Description Reset Access SRXREQ Target Receive Request. This bit asserts whenever the target receive FIFO is not empty. Read or flush the target receive FIFO to clear this bit. This bit asserts on the falling edge of the I2C_SCL clock pulse that clocks in the last data bit of a byte.
  • Page 233 Reference Manual ADuCM356 REGISTER DETAILS: I Table 297. Bit Descriptions for ID0 Bits Bit Name Settings Description Reset Access [15:8] Reserved Reserved. [7:0] Target Device ID 0. ID0, Bits[7:1] are programmed with the device ID. ID0, Bit 0 is don't care. See SCTL, Bit 1 to see how this register is programmed with a 10-bit address.

  • Page 234: Second Target Address Device Id Register

    Reference Manual ADuCM356 REGISTER DETAILS: I SECOND TARGET ADDRESS DEVICE ID REGISTER Address: 0x40003040, Reset: 0x0000, Name: ID1 Table 298. Bit Descriptions for ID1 Bits Bit Name Settings Description Reset Access [15:8] Reserved Reserved. [7:0] Target Device ID 1. ID1, Bits[7:1] are programmed with the device ID. ID1, Bit 0 is don't care. See SCTL, Bit 1 to see how this register is programmed with a 10-bit address.

  • Page 235: Initiator And Target Shared Control Register

    Reference Manual ADuCM356 REGISTER DETAILS: I Table 301. Bit Descriptions for FSTAT (Continued) Bits Bit Name Settings Description Reset Access 01 1 byte in the FIFO. 10 2 bytes in the FIFO. 11 Reserved. [3:2] SRXF Target Receive FIFO Status. The status is a count of the number of bytes in a FIFO.
  • Page 236 Reference Manual ADuCM356 REGISTER DETAILS: I Table 303. Bit Descriptions for ASTRETCH_SCL (Continued) 15: 8 + DIV 7: 4 − 1 7: 4 ASTRETCH_SCL × 2 Bits Bit Name Settings Description Reset Access 1 13: 8 − CTL 1 13: 8...

  • Page 237: Serial Peripheral Interfaces

    (also known as full duplex). The two SPIs implemented on the ADuCM356 can operate to a maximum bit rate of 6.5 Mbps in In initiator mode, the SPIx_CTL register controls the polarity and both initiator and target modes.

  • Page 238: Spi Transfer Initiation

    If SPIx_CNT, Bit 15 is set, a new frame starts after every SPIx_CNT, Bits[13:0] number of bytes. Multiples of bytes in If an ADuCM356 initiator wants to communicate with multiple SPI SPIx_CNT, Bits[13:0] are always transferred in this case. If there is targets, GPIOs can be connected to the chip select lines of the no data or space in the FIFO, the transfer stalls until it is available.
  • Page 239 Reference Manual ADuCM356 SERIAL PERIPHERAL INTERFACES Figure 61. SPI Transfer Protocol, CPHA = 0 Figure 62. SPI Transfer Protocol, CPHA = 1 Transfers in Target Mode Full Duplex Operation In target mode, a transfer is initiated by the assertion of the chip Simultaneous reads and writes are supported on the SPI.

  • Page 240: Spi Interrupts

    Reference Manual ADuCM356 SERIAL PERIPHERAL INTERFACES In addition, the SPI0 and SPI1 interrupt source must be enabled in SPI INTERRUPTS the NVIC register as follows: ISER0, Bit 15 = SPI0, ISER0, Bit 16 = There is one interrupt line per SPI and 11 sources of interrupts.

  • Page 241: Spi Cserr Condition

    Reference Manual ADuCM356 SERIAL PERIPHERAL INTERFACES resistor is required when this feature is selected. The wire-OR bit DMA Initiator Transmit Configuration (SPIx_CTL, Bit 4) controls the pad enable outputs for the data lines. The DMA SPI transmit channel must be configured. Configure the SPI CSERR CONDITION NVIC to enable DMA transmit initiator interrupts.

  • Page 242: Spi And Power-Down Modes

    Reference Manual ADuCM356 SERIAL PERIPHERAL INTERFACES able receive DMA request. SPI_CNT.VALUE = XXX; //number of bytes to be received. A = SPI_RX; //dummy read. The DMA transfer stops when the appropriate number of clock cycles have been generated. All DMA data transfers are 16-bit transfers.

  • Page 243: Register Summary: Spi0/Spi1

    Reference Manual ADuCM356 REGISTER SUMMARY: SPI0/SPI1 Table 305. SPI Register Summary Address Name Description Reset Access 0x40004000 SPI0_STAT Status 0x0800 0x40004004 SPI0_RX Receive 0x0000 0x40004008 SPI0_TX Transmit 0x0000 0x4000400C SPI0_DIV Baud rate selection 0x0000 0x40004010 SPI0_CTL Configuration 0x0000 0x40004014 SPI0_IEN...

  • Page 244: Register Details: Spi0/Spi1

    Reference Manual ADuCM356 REGISTER DETAILS: SPI0/SPI1 STATUS REGISTERS Address: 0x40004000, Reset: 0x0800, Name: SPI0_STAT Address: 0x40024000, Reset: 0x0800, Name: SPI1_STAT Table 306. Bit Descriptions for SPI0_STAT, SPI1_STAT Bits Bit Name Settings Description Reset Access Detected an Edge on Ready Indicator for Flow Control. This bit indicates that there was an active edge R/W1C on the P0.3 line depending on the flow control mode.

  • Page 245: Receive Registers

    Reference Manual ADuCM356 REGISTER DETAILS: SPI0/SPI1 Table 306. Bit Descriptions for SPI0_STAT, SPI1_STAT (Continued) Bits Bit Name Settings Description Reset Access TXEMPTY SPI Transmit FIFO Empty Interrupt. R/W1C 0 Cleared to 0 when 1 is written to this bit or when SPIx_CTL, Bit 0 is cleared to 0.
  • Page 246 Reference Manual ADuCM356 REGISTER DETAILS: SPI0/SPI1 Table 310. Bit Descriptions for SPI0_CTL, SPI1_CTL Bits Bit Name Settings Description Reset Access Reserved Reserved. CSRST Reset Mode for Chip Select Error Bit. 0 The bit counter continues from where it stopped. The SPI can receive the remaining bits when the chip select is asserted and user code must ignore the SPIx_STAT, Bit 12 interrupt.

  • Page 247: Interrupt Configuration Registers

    Reference Manual ADuCM356 REGISTER DETAILS: SPI0/SPI1 Table 310. Bit Descriptions for SPI0_CTL, SPI1_CTL (Continued) Bits Bit Name Settings Description Reset Access 1 Serial clock pulses at the beginning of each serial bit transfer. MASEN Initiator Mode Enable. 0 Enable target mode.

  • Page 248: Transfer Byte Count Registers

    Reference Manual ADuCM356 REGISTER DETAILS: SPI0/SPI1 Table 311. Bit Descriptions for SPI0_IEN, SPI1_IEN (Continued) Bits Bit Name Settings Description Reset Access 001 Transmit interrupt occurs when 2 bytes have been transferred. Receive interrupt occurs when 2 or more bytes have been received into the FIFO.

  • Page 249: Fifo Status Registers

    Reference Manual ADuCM356 REGISTER DETAILS: SPI0/SPI1 Table 313. Bit Descriptions for SPI0_DMA, SPI1_DMA (Continued) Bits Bit Name Settings Description Reset Access 0 Disable transmit DMA interrupt. 1 Enable transmit DMA interrupt. Enable DMA for Data Transfer. Set by user code to start a DMA transfer. Cleared by user code at the end of DMA transfer.

  • Page 250: Flow Control Registers

    Reference Manual ADuCM356 REGISTER DETAILS: SPI0/SPI1 Table 315. Bit Descriptions for SPI0_RD_CTL, SPI1_RD_CTL (Continued) Bits Bit Name Settings Description Reset Access is driven by the initiator during the transmit phase. After a wait time of SPI_WAIT_TMR SCLK cycles, the target is expected to drive the same MOSI pin. Program SPI_FLOW_CTL, Bits[1:0] to 01 to introduce wait states for allowing turnaround time.
  • Page 251 Reference Manual ADuCM356 REGISTER DETAILS: SPI0/SPI1 Table 316. Bit Descriptions for SPI0_FLOW_CTL, SPI1_FLOW_CTL (Continued) Bits Bit Name Settings Description Reset Access [1:0] MODE Flow Control Mode. Flow control configuration for data reads. When the P0.3 signal is used for flow control, P0.3 can be any control signal that is tied to this P0.3 input of the SPI module.

  • Page 252: Wait Timer For Flow Control Registers

    Reference Manual ADuCM356 REGISTER DETAILS: SPI0/SPI1 WAIT TIMER FOR FLOW CONTROL REGISTERS Address: 0x4000402C, Reset: 0x0000, Name: SPI0_WAIT_TMR Address: 0x4002402C, Reset: 0x0000, Name: SPI1_WAIT_TMR This register is only used in initiator mode. Table 317. Bit Descriptions for SPI0_WAIT_TMR, SPI1_WAIT_TMR Bits...

  • Page 253: Uart Serial Interface

    This mode puts certain constraints on the software itself in that the software must respond within a certain time to The ADuCM356 features an industry-standard 16450 UART or prevent overflow errors from occurring in the receive channel. 16550 UART peripheral with support for DMA.
  • Page 254 Reference Manual ADuCM356 UART SERIAL INTERFACE FIFO Mode (16550 UART) Automatic Baud Rate Detection The 16-byte deep transmit FIFO and receive FIFO are implement- The automatic baud detection (ABD) block is used to match the ed. Therefore, the UART is compatible with the industry-standard baud rates of two UART devices automatically.
  • Page 255 Recommendations for UART Receive Wake-Up from Hibernate Mode If the UART receive input is used to wake the ADuCM356 from hibernate mode, keep in mind that the UART block, along with the rest of the ADuCM356 chip, requires 10 μs settling time after the first falling edge of the UART wake-up byte.

  • Page 256: Register Summary: Uart

    Reference Manual ADuCM356 REGISTER SUMMARY: UART Table 320. UART Register Summary Address Name Description Reset Access 0x40005000 COMTX Transmit holding 0x0000 0x40005000 COMRX Receive buffer 0x0000 0x40005004 COMIEN Interrupt enabler 0x0000 0x40005008 COMIIR Interrupt identification 0x0001 0x4000500C COMLCR Line control...

  • Page 257: Register Details: Uart

    Reference Manual ADuCM356 REGISTER DETAILS: UART TRANSMIT HOLDING REGISTER Address: 0x40005000, Reset: 0x0000, Name: COMTX COMRX and COMTX share the same address although they are implemented as different registers. If these registers are written to, the user accesses the transmit holding register (COMTX). If these registers are read from, the user accesses the receive buffer register (COMRX).

  • Page 258: Interrupt Identification Register

    Reference Manual ADuCM356 REGISTER DETAILS: UART INTERRUPT IDENTIFICATION REGISTER Address: 0x40005008, Reset: 0x0001, Name: COMIIR Table 324. Bit Descriptions for COMIIR Bits Bit Name Settings Description Reset Access [15:8] Reserved Reserved. [7:6] FEND FIFO Enabled. 00 FIFO not enabled, 16450 UART mode.

  • Page 259: Modem Control Register

    Reference Manual ADuCM356 REGISTER DETAILS: UART MODEM CONTROL REGISTER Address: 0x40005010, Reset: 0x0000, Name: COMMCR Table 326. Bit Descriptions for COMMCR Bits Bit Name Settings Description Reset Access [15:5] Reserved Reserved. LOOPBACK Loopback Mode. In loopback mode, the UART_SOUT is forced high. The modem signals are also directly connected to the status inputs (RTS in COMMCR to CTS in COMMSR, DTR in COMMCR to DSR in COMMSR, OUT1 in COMMCR to RI in COMMSR, and OUT2 in COMMCR to DCD in COMMSR).

  • Page 260: Modem Status Register

    Reference Manual ADuCM356 REGISTER DETAILS: UART Table 327. Bit Descriptions for COMLSR (Continued) Bits Bit Name Settings Description Reset Access 0 Receive data has not been overwritten. 1 Receive data was overwritten by new data before COMRX was read. Data Ready. This bit is cleared only by reading COMRX. If set, this bit does not self clear.

  • Page 261: Fractional Baud Rate Register

    Reference Manual ADuCM356 REGISTER DETAILS: UART Table 330. Bit Descriptions for COMFCR (Continued) Bits Bit Name Settings Description Reset Access FDMAMD FIFO DMA Mode. 0 Receive DMA request is asserted when there is data in RBR in the COMRX register or the receive FIFO, and deasserts when RBR or the receive FIFO is empty.

  • Page 262: Uart Control Register

    Reference Manual ADuCM356 REGISTER DETAILS: UART UART CONTROL REGISTER Address: 0x40005030, Reset: 0x0100, Name: COMCTL Table 334. Bit Descriptions for COMCTL Bits Bit Name Settings Description Reset Access [15:8] UART Revision ID. [7:5] Reserved Reserved. RXINV Invert Receiver Line. 0 Do not invert receiver line (idling high).

  • Page 263: Autobaud Control Register

    Reference Manual ADuCM356 REGISTER DETAILS: UART AUTOBAUD CONTROL REGISTER Address: 0x40005040, Reset: 0x0000, Name: COMACR Table 338. Bit Descriptions for COMACR Bits Bit Name Reserved Description Reset Access [15:12] Reserved Reserved. [11:8] Ending Edge Count. 0000 First edge. 0001 Second edge.

  • Page 264: Digital Die General-Purpose Timers

    1, 4, 16, or 256. Free running mode and periodic mode FEATURES are available. The timers have a capture events feature, with the The ADuCM356 digital die integrates three identical general-pur- capability to capture 32 different events on each timer. See Figure pose, 16-bit count up or count down timers: Timer 0, Timer 1, and for an overview of the general-purpose timers.
  • Page 265 Reference Manual ADuCM356 DIGITAL DIE GENERAL-PURPOSE TIMERS Interval = (GPTx_LOAD × Prescaler)/Clock Source The value of a counter can be read at any time by accessing (29) ► its value register (GPTx_CURCNT). In an asynchronous configu- For example, if GPTx_LOAD = 0x100, prescaler = 4, and clock ration, GPTx_CURCNT must always be read twice.
  • Page 266 Reference Manual ADuCM356 DIGITAL DIE GENERAL-PURPOSE TIMERS General-Purpose Timers Power Gating To limit power consumption, the general-purpose timers are pow- ered off with the clock input disabled. To enable the clock input to each of the general-purpose timer blocks, clear the appropriate bit in the CTL5 register.

  • Page 267: Register Summary: General-Purpose Timers

    Reference Manual ADuCM356 REGISTER SUMMARY: GENERAL-PURPOSE TIMERS Table 342. Timer Register Summary Address Name Description Reset Access 0x40000000 GPT0_LOAD 16-bit synchronous load value 0x0000 0x40000004 GPT0_CURCNT 16-bit timer synchronous value 0x0000 0x40000008 GPT0_CTL Control 0x000A 0x4000000C GPT0_CLRINT Clear interrupt 0x0000...

  • Page 268: Register Details: General-Purpose Timers

    Reference Manual ADuCM356 REGISTER DETAILS: GENERAL-PURPOSE TIMERS 16-BIT SYNCHRONOUS LOAD VALUE REGISTERS Address: 0x40000000, Reset: 0x0000, Name: GPT0_LOAD Address: 0x40000400, Reset: 0x0000, Name: GPT1_LOAD Address: 0x40000800, Reset: 0x0000, Name: GPT2_LOAD Table 343. Bit Descriptions for GPT0_LOAD, GPT1_LOAD, GPT2_LOAD Bits Bit Name...

  • Page 269: Clear Interrupt Registers

    Reference Manual ADuCM356 REGISTER DETAILS: GENERAL-PURPOSE TIMERS Table 345. Bit Descriptions for GPT0_CTL, GPT1_CTL, GPT2_CTL (Continued) Bits Bit Name Settings Description Reset Access Timer Enable. Used to enable and to disable the timer. Clearing this bit resets the timer, including the GPTx_CURCNT register.

  • Page 270: 16-Bit Asynchronous Load Value Registers

    Reference Manual ADuCM356 REGISTER DETAILS: GENERAL-PURPOSE TIMERS 16-BIT ASYNCHRONOUS LOAD VALUE REGISTERS Address: 0x40000014, Reset: 0x0000, Name: GPT0_ALOAD Address: 0x40000414, Reset: 0x0000, Name: GPT1_ALOAD Address: 0x40000814, Reset: 0x0000, Name: GPT2_ALOAD Table 348. Bit Descriptions for GPT0_ALOAD, GPT1_ALOAD, GPT2_ALOAD Bits Bit Name...
  • Page 271 Reference Manual ADuCM356 REGISTER DETAILS: GENERAL-PURPOSE TIMERS Table 350. Bit Descriptions for GPT0_STAT, GPT1_STAT, GPT2_STAT (Continued) Bits Bit Name Settings Description Reset Access 0 No timeout event has occurred. 1 A timeout event has occurred. analog.com Rev. A | 271 of 312...

  • Page 272: Analog Die General-Purpose Timers

    AFE general-purpose timer interrupts. AFE PWM The AFE die in the ADuCM356 has a dedicated PWM output feature. The high period for the PWM is the difference between the values in the timer load register and either the PWMMAT0 register or PWMMATCH register.

  • Page 273: Register Summary: Analog Die General-Purpose Timers

    Reference Manual ADuCM356 REGISTER SUMMARY: ANALOG DIE GENERAL-PURPOSE TIMERS Table 351. AGPT0 Register Summary Address Name Description Reset Access 0x400C0D00 16-bit load value 0x0000 0x400C0D04 VAL0 16-bit timer value 0x0000 0x400C0D08 CON0 Control 0x000A 0x400C0D0C CLRI0 Clear interrupt 0x0000 0x400C0D14...

  • Page 274: Register Details: Analog Die General-Purpose Timers

    Reference Manual ADuCM356 REGISTER DETAILS: ANALOG DIE GENERAL-PURPOSE TIMERS 16-BIT LOAD VALUE REGISTER Address: 0x400C0D00, Reset: 0x0000, Name: LD0 Table 353. Bit Descriptions for LD0 Bits Bit Name Settings Description Reset Access [15:0] LOAD Load Value. The up or down counter is periodically loaded with this value if periodic mode is selected (CON0, Bit 3 = 1).

  • Page 275: Clear Interrupt Register

    Reference Manual ADuCM356 REGISTER DETAILS: ANALOG DIE GENERAL-PURPOSE TIMERS Table 355. Bit Descriptions for CON0 (Continued) Bits Bit Name Settings Description Reset Access Count Up. Used to control whether the timer increments (counts up) or decrements (counts down) the up or down counter.

  • Page 276: Pwm Control Register

    Reference Manual ADuCM356 REGISTER DETAILS: ANALOG DIE GENERAL-PURPOSE TIMERS Table 359. Bit Descriptions for STA0 Bits Bit Name Settings Description Reset Access [15:9] Reserved Reserved. RSTCNT Counter Reset Occurring. Indicates that the counter is currently being reset due to an event detection.

  • Page 277: 16-Bit Load Value Register

    Reference Manual ADuCM356 REGISTER DETAILS: ANALOG DIE GENERAL-PURPOSE TIMERS Table 362. Bit Descriptions for INTEN Bits Bit Name Settings Description Reset Access [15:1] Reserved Reserved. INTEN Interrupt Enable. This value is used when the PWM is operating in match mode. The PWM output is asserted when the up or down counter is equal to this match value.

  • Page 278: Clear Interrupt Register

    Reference Manual ADuCM356 REGISTER DETAILS: ANALOG DIE GENERAL-PURPOSE TIMERS Table 365. Bit Descriptions for CTL (Continued) Bits Bit Name Settings Description Reset Access Timer Enable. Used to enable and disable the timer. Clearing this bit resets the timer, including the CURCNT register.

  • Page 279: Status Register

    Reference Manual ADuCM356 REGISTER DETAILS: ANALOG DIE GENERAL-PURPOSE TIMERS Table 368. Bit Descriptions for ACURCNT Bits Bit Name Settings Description Reset Access [15:0] VALUE Counter Value. Reflects the current up or down counter value. Reading this register takes advantage of having the timer run on PCLK by bypassing clock synchronization logic that is otherwise required.
  • Page 280 Reference Manual ADuCM356 REGISTER DETAILS: ANALOG DIE GENERAL-PURPOSE TIMERS Table 371. Bit Descriptions for PWMMATCH (Continued) Bits Bit Name Settings Description Reset Access when a timeout event occurs. If the match value is never reached, or occurs simultaneous to a timeout event, the PWM output remains idle.

  • Page 281: Afe Watchdog Timer

    Reference Manual ADuCM356 AFE WATCHDOG TIMER Therefore, the reset output can work with all the power-down WATCHDOG TIMER FEATURES AND BLOCK modes, including hibernate mode. DIAGRAM In MCU software debugging mode, disable the WDT first before To satisfy the IEC 61508 standard requirement for separating the software debugging.

  • Page 282: Interrupt Mode

    INTERRUPT MODE If a watchdog reset occurs while debugging via the SWD port, com- munications between the debugger and the ADuCM356 can be lost. As such, while debugging, the user can optionally configure the watchdog timer to generate an interrupt instead of a reset. Enable this feature only during code development and debug.

  • Page 283: Register Summary: Afe Watchdog Timer

    Reference Manual ADuCM356 REGISTER SUMMARY: AFE WATCHDOG TIMER Table 372. AFEWDT Register Summary Address Name Description Reset Access 0x400C0900 WDTLD Watchdog timer load value 0x1000 0x400C0904 WDTVALS Current count value 0x1000 0x400C0908 WDTCON Watchdog timer control 0x00C9 0x400C090C WDTCLRI Refresh watchdog...

  • Page 284: Register Details: Afe Watchdog Timer

    Reference Manual ADuCM356 REGISTER DETAILS: AFE WATCHDOG TIMER WATCHDOG TIMER LOAD VALUE REGISTER Address: 0x400C0900, Reset: 0x1000, Name: WDTLD Table 373. Bit Descriptions for WDTLD Bits Bit Name Settings Description Reset Access [15:0] LOAD Watchdog Timer Load Value. This user programmable value is the value that the counter starts from 0x1000 before counting down to 0.

  • Page 285: Refresh Watchdog Register

    Reference Manual ADuCM356 REGISTER DETAILS: AFE WATCHDOG TIMER Table 375. Bit Descriptions for WDTCON (Continued) Bits Bit Name Settings Description Reset Access WDT Interrupt Enable. 0 Watchdog timer timeout creates a reset. 1 Watchdog timer timeout creates an interrupt instead of a reset.

  • Page 286: Minimum Load Value Register

    Reference Manual ADuCM356 REGISTER DETAILS: AFE WATCHDOG TIMER MINIMUM LOAD VALUE REGISTER Address: 0x400C091C, Reset: 0x0800, Name: WDTMINLD Watchdog timer minimum timeout period. Lower window limit. Table 378. Bit Descriptions for WDTMINLD Bits Bit Name Settings Description Reset Access [15:0] MIN_LOAD WDT Minimum Load Value.

  • Page 287: Digital Die Wake-Up Timer

    The digital die WUT is the highest priority interrupt on the To enable periodic interrupts, perform the following steps: ADuCM356, as described in Table 41. The WUT is also one of four interrupt sources that can wake the digital die from hibernate 1.

  • Page 288: Wut Operating Modes

    Reference Manual ADuCM356 DIGITAL DIE WAKE-UP TIMER Figure 65. Digital Die WUT Block Diagram WUT OPERATING MODES Snapshot of the Timer Counter The CPU can instruct the timer to take a snapshot of its elapsed Initial WUT Power-Up time count by writing a software key of 0x7627 to the GWY regis- ter.

  • Page 289: Register Summary: Digital Die Wake-Up Timer

    Reference Manual ADuCM356 REGISTER SUMMARY: DIGITAL DIE WAKE-UP TIMER Table 379. WUT Register Summary Address Name Description Reset Access 0x40001400 Control 0 0x03C4 0x40001404 Status 0 0x7F88 0x40001408 Status 1 0x0078 0x4000140C CNT0 Count 0 0x0000 0x40001410 CNT1 Count 1...

  • Page 290: Register Details: Digital Die Wake-Up Timer

    Reference Manual ADuCM356 REGISTER DETAILS: DIGITAL DIE WAKE-UP TIMER CONTROL 0 REGISTER Address: 0x40001400, Reset: 0x03C4, Name: CR0 CR0 is the primary of two control registers for the WUT, the other being CR1. All mainstream WUT operations are enabled and disabled by the CPU using CR0.

  • Page 291: Status 0 Register

    Reference Manual ADuCM356 REGISTER DETAILS: DIGITAL DIE WAKE-UP TIMER Table 380. Bit Descriptions for CR0 (Continued) Bits Bit Name Settings Description Reset Access Reserved Reserved. Clear to 0. ALMINTEN Enable ALMINT Sourced Alarm Interrupts to the CPU. ALMINTEN gives the CPU extra control over whether an alarm event (alarm count matches the WUT count) triggers an interrupt.
  • Page 292 Reference Manual ADuCM356 REGISTER DETAILS: DIGITAL DIE WAKE-UP TIMER Table 381. Bit Descriptions for SR0 (Continued) Bits Bit Name Settings Description Reset Access 1 Results of a posted write are visible to the CPU. WSYNCCNT0 Synchronization Status of Posted Writes to the CNT0 Register. WSYNCCNT0 indicates if the effects of a posted write to CNT0 are visible to the CPU.

  • Page 293: Status 1 Register

    Reference Manual ADuCM356 REGISTER DETAILS: DIGITAL DIE WAKE-UP TIMER Table 381. Bit Descriptions for SR0 (Continued) Bits Bit Name Settings Description Reset Access and CNT0, at a displacement of MOD60ALM increments past a modulo 60 boundary. Cleared by writing 1 to this bit.

  • Page 294: Count 0 Register

    Reference Manual ADuCM356 REGISTER DETAILS: DIGITAL DIE WAKE-UP TIMER Table 382. Bit Descriptions for SR1 (Continued) Bits Bit Name Settings Description Reset Access 1 A previously posted write to CR0 is still awaiting execution. No new posting to this MMR can be accepted.

  • Page 295: Alarm 1 Register

    Reference Manual ADuCM356 REGISTER DETAILS: DIGITAL DIE WAKE-UP TIMER ALARM 1 REGISTER Address: 0x40001418, Reset: 0xFFFF, Name: ALM1 ALM1 contains the upper 16 bits of the prescaled nonfractional WUT alarm target time value, where the overall alarm is defined as ALM1, ALM0, and ALM2.

  • Page 296: Status 2 Register

    Reference Manual ADuCM356 REGISTER DETAILS: DIGITAL DIE WAKE-UP TIMER Table 388. Bit Descriptions for CR1 (Continued) Bits Bit Name Settings Description Reset Access MMRs. In contrast, RTC1 can prescale the clock by any power of two in the interval Bits[15:0] to use as its time base.
  • Page 297 Reference Manual ADuCM356 REGISTER DETAILS: DIGITAL DIE WAKE-UP TIMER Table 389. Bit Descriptions for SR2 (Continued) Bits Bit Name Settings Description Reset Access 1 Results of a posted write to CR1 are visible to the CPU. WSYNCCR1MIR Synchronization Status of Posted Writes to CR1. This bit indicates if the effects of a posted write to CR1 are visible to the CPU.

  • Page 298: Snapshot 0 Register

    Reference Manual ADuCM356 REGISTER DETAILS: DIGITAL DIE WAKE-UP TIMER Table 389. Bit Descriptions for SR2 (Continued) Bits Bit Name Settings Description Reset Access CNTROLLINT WUT Count Roll Over Interrupt Source. This bit sticks active high when the CNT1 and CNT0...

  • Page 299: Modulo Register

    Reference Manual ADuCM356 REGISTER DETAILS: DIGITAL DIE WAKE-UP TIMER Table 392. Bit Descriptions for SNAP2 Bits Bit Name Settings Description Reset Access Reserved Reserved. [14:0] VALUE Contains a Sticky Snapshot of CNT2. This channel takes a sticky snapshot of the 47-bit WUT count in CNT1, CNT0, and CNT2 and stores it in SNAP1, SNAP0, and SNAP2, respectively.
  • Page 300 Reference Manual ADuCM356 REGISTER DETAILS: DIGITAL DIE WAKE-UP TIMER Table 394. Bit Descriptions for CNT2 Bits Bit Name Settings Description Reset Access Reserved Reserved. [14:0] VALUE Fractional Bits of the WUT Real-Time Count. CNT2 contains the fractional part of the WUT count, where the count is denominated in prescaled time units and is given by CNT1, CNT0, and CNT2.

  • Page 301: Alarm 2 Register

    Reference Manual ADuCM356 REGISTER DETAILS: DIGITAL DIE WAKE-UP TIMER ALARM 2 REGISTER Address: 0x40001444, Reset: 0x0000, Name: ALM2 ALM2 specifies the fractional nonprescaled bits of the WUT alarm target time value, down to an individual 32 kHz clock cycle, where the overall alarm is defined as ALM1, ALM0, and ALM2.
  • Page 302 Reference Manual ADuCM356 REGISTER DETAILS: DIGITAL DIE WAKE-UP TIMER Table 396. Bit Descriptions for SR6 (Continued) Bits Bit Name Settings Description Reset Access 10 The next read of CNTx is the third in a triple read sequence and returns the snapshot of CNT2 that was taken when the first read of CNTx in the sequence occurred.

  • Page 303: Cyclic Redundancy Check

    CRC FUNCTIONAL DESCRIPTION CRC FEATURES The following sections detail the functionality of the CRC. Control The CRC, used by the ADuCM356 MCU, supports the following for address decrementation and incrementation options for comput- features: ing the CRC on a block of memory is in the DMA controller, Generation of a CRC signature for a block of data.
  • Page 304 Reference Manual ADuCM356 CYCLIC REDUNDANCY CHECK Table 397. 16-Bit Polynomial Programming Register Format, MSB First Calculation Register Bit(s) Value CRC Polynomial Register (POLY) [31:24] 0001 0000 [23:16] 0010 0001 [15:8] 0x08B0 [7:0] 0x08B0 CRC Result Register (Result) [31:24] [23:16] Result...
  • Page 305 Reference Manual ADuCM356 CYCLIC REDUNDANCY CHECK Table 399. 8-Bit Polynomial Programming Register Format, MSB First Calculation (Continued) Register Bit(s) Value [7:0] 0x08B0 Initial Seed Programmed in CRC Result Register (Result) [31:24] CRC seed [23:16] 0x08B0 [15:8] 0x08B0 [7:0] 0x08B0 + x + 1 = 1000 0011 (1) = 0x83 where the smallest exponent (x term) is implied.

  • Page 306: Crc Data Transfer

    Reference Manual ADuCM356 CYCLIC REDUNDANCY CHECK CRC DATA TRANSFER The data stream can be written to the block using the DMA control- ler or by using the MCU directly. CRC INTERRUPTS AND EXCEPTIONS The DMA channel generates an interrupt upon completion of data transfer to the CRC block.
  • Page 307 Reference Manual ADuCM356 CYCLIC REDUNDANCY CHECK more information about programming the DMA, see the DMA Access Steps Controller section. A DMA_DONE interrupt signal of the DMA The CRC accelerator block supports software DMA. To access the channel indicates the completion of data transfer to the CRC DMA, take the following steps: block.

  • Page 308: Register Summary: Crc

    Reference Manual ADuCM356 REGISTER SUMMARY: CRC Table 404. CRC Register Summary Address Name Description Reset Access 0x40040000 CRC control register 0x10000000 0x40040004 IPDATA Input data word register 0x00000000 0x40040008 RESULT CRC result register 0x00000000 0x4004000C POLY Programmable CRC polynomial 0x04C11DB7...

  • Page 309: Register Details: Crc

    Reference Manual ADuCM356 REGISTER DETAILS: CRC CRC CONTROL REGISTER Address: 0x40040000, Reset: 0x10000000, Name: CTL Table 405. Bit Descriptions for CTL Bits Bit Name Settings Description Reset Access [31:28] REVID Revision ID. [27:5] Reserved Reserved. W16SWP Word 16 Swap. This bit swaps 16-bit half words within a 32-bit word.

  • Page 310: Input Data Byte Register

    Reference Manual ADuCM356 REGISTER DETAILS: CRC Table 409. Bit Descriptions for IPBITSN Bits Bit Name Settings Description Reset Access [7:0] DATA_BITS Input Data Bits. These fields are used to calculate CRC data byte from 1 bit to 7 bits of input data.

  • Page 311: Hardware Design Considerations

    ADuCM356 HARDWARE DESIGN CONSIDERATIONS TYPICAL SYSTEM CONFIGURATION Figure 67. ADuCM356 Typical System Configuration SERIAL WIRE DEBUG INTERFACE The SWD interface provides a debug port for pin limited packages. The SWD replaces the 5-pin JTAG port with the SWCLK pin and a single bidirectional data pin (SWDIO), providing all the normal JTAG debug and test functionality.

  • Page 312: Rev. A | 6 Of

    Evaluation Board until you have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) and Analog Devices, Inc. (“ADI”), with its principal place of business at Subject to the terms and conditions of the Agreement, ADI hereby grants to Customer a free, limited, personal, temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY.

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