Analog Devices ADSP-SC58 Series Hardware Reference Manual page 3530

Sharc+ processor
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Data Structures
The contents are packed as follows:
ADI_ROM_OTP_DMC_CONFIG::
ulDDR_MREMR1
[15:0]
[31:16]
ulDDR_TR0
Content of
DMC_TR0
ulDDR_TR1
Content of
DMC_TR1
ulDDR_TR2
Content of
DMC_TR2
ulDDR_PHYCTL0
Content of
DMC_PHY_CTL0
ulDDR_PHYCTL145
Packed content of
The contents are packed as follows:
ADI_ROM_OTP_DMC_CONFIG::
ulDDR_PHYCTL145
[7:0]
[15:8]
[31:16]
ulDDR_PHYCTL2
Content of
DMC_PHY_CTL2
ulDDR_PHYCTL3
Content of
DMC_PHY_CTL3
ulDDR_CAL_PADCTL0_PHY_STAT3_0
Packed content of
The contents are packed as follows:
53–110
Register
DMC_EMR1
DMC_MR
,
DMC_PHY_CTL1
DMC_PHY_CTL4
Register
DMC_PHY_CTL5[7:0]
DMC_PHY_CTL4[7:0]
DMC_PHY_CTL1[31:16]
DMC_CAL_PADCTL0
[15:0]
[15:0]
and DMC_PHY_CTL5 registers.
, DMC_PHY_STAT0 , and DMC_PHY_STAT3 registers.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference

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Adsp-2158 series

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