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4.5 Wait Function
4.5.1 Programmable wait function
To facilitate interfacing with low-speed memories and I/O devices, up to 3 data waits can be inserted in a bus
cycle that starts every two memory blocks.
The number of waits can be programmed by using the data wait control register (DWC). Immediately after the
system has been reset, a state in which three data waits are inserted is automatically programmed for all memory
blocks.
(1) Data wait control register (DWC)
This register can be read/written in 16-bit units.
After reset: FFFFH
R/W
Symbol
15
14
13
DW61
DW71
DW70
DWC
DWn1
DWn0
0
0
0
1
1
0
1
1
n
0
Blocks 0/1
1
Blocks 2/3
2
Blocks 4/5
3
Blocks 6/7
4
Blocks 8/9
5
Blocks 10/11
6
Blocks 12/13
7
Blocks 14/15
Block 0 is reserved for the internal ROM area. It is not subject to programmable wait control, regardless of the
setting of DWC, and is always accessed without wait states.
The internal RAM area of block 15 is not subject to programmable wait control and is always accessed without
wait states. The on-chip peripheral I/O area of this block is not subject to programmable wait control either; only
wait control from each peripheral function is performed.
132
CHAPTER 4
BUS CONTROL FUNCTION
Address: FFFFF060H
12
11
10
9
DW60
DW51
DW50
DW41
Number of wait states to be inserted
Blocks into which wait states are inserted
User's Manual U13850EJ6V0UD
8
7
6
5
DW40
DW31
DW30
DW21
DW20
0
1
2
3
4
3
2
1
DW11
DW10
DW01
DW00
0
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