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4.6 Wait Function
4.6.1 Programmable wait function
(1) Data wait control registers 0, 1 (DWC0, DWC1)
To facilitate interfacing with low-speed memory and I/Os, it is possible to insert up to 7 data wait states in the
starting bus cycle for each CS space.
The number of wait states can be specified by program using data wait control registers 0 and 1 (DWC0,
DWC1). Just after system reset, all blocks have 7 data wait states inserted.
These registers can be read/written in 16-bit units.
Cautions 1. The internal ROM area and internal RAM area are not subject to programmable waits
and ordinarily no wait access is carried out. The on-chip peripheral I/O area is also not
subject to programmable wait states, with wait control performed by each peripheral
function only.
2. In the following cases, the settings of registers DWC0 and DWC1 are invalid (wait
control is performed by each memory controller).
• • • • Page ROM on-page access
• • • • EDO DRAM access
• • • • SDRAM access
3. Write to the DWC0 and DWC1 registers after reset, and then do not change the set
values.
initialization routine until the initial setting of the DWC0 and DWC1 registers is
complete. However, it is possible to access external memory areas whose initialization
settings are complete.
CHAPTER 4
BUS CONTROL FUNCTION
Also, do not access an external memory area other than the one for this
User's Manual U14359EJ4V0UM
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