Bus Hold Procedure; Operation In Power Save Mode - NEC V850E/MS1 UPD703100 User Manual

4.8.2 Bus hold procedure

The procedure of the bus hold function is illustrated below.
<1> HLDRQ = 0 accepted
<2> All bus cycle start request pending
<3> End of current bus cycle
<4> Transition to bus idle state
<5> HLDAK = 0
<6> HLDRQ = 1 accepted
<7> HLDAK = 1
<8> Clears bus cycle start request pending
<9> Start of bus cycle
HLDRQ (Input)
HLDAK (Output)

4.8.3 Operation in power save mode

In the STOP or IDLE mode, the internal system clock is stopped. Consequently, the bus hold state is not accepted
and set even if the HLDRQ pin becomes active.
In the HALT mode, the HLDAK pin immediately becomes active when the HLDRQ pin becomes active, and the bus
hold state is set. When the HLDRQ pin becomes inactive, the HLDAK pin becomes inactive. As a result, the bus hold
state is cleared, and the HALT mode is set again.
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CHAPTER 4 BUS CONTROL FUNCTION
<1> <2> <3><4><5>
User's Manual U12688EJ4V0UM00
Normal state
Bus hold state
Normal state
<6> <7><8><9>