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6.5 Power Save Control
6.5.1 General
The V854 is provided with the following power save or standby modes to reduce power consumption when CPU
operation is not required.
(1) HALT mode
In this mode, the clock generator (oscillator and PLL synthesizer) continues operation but the operating clock
of the CPU stops. The internal peripherals continue to function in reference to the internal system clock. Total
power consumption of the system can be reduced through intermittent operation between normal operation
and HALT modes.
A dedicated instruction (HALT instruction) transfers to the V854 to the HALT mode.
(2) IDLE mode
In this mode, both the CPU clock and the internal system clock are stopped to further reduce power con-
sumption. However, since the clock generator continues to run, normal operation can resume without having
to wait for the oscillator and PLL circuits to stabilize.
Setting the PSC register, which is a specific register, transfers the V854 to the IDLE mode.
The IDLE mode is somewhere between the STOP and HALT modes in terms of clock stabilization time and
power consumption, and is used in applications where the clock oscillation time should be eliminated but low
power consumption is required.
Caution When inputting external clocks, continue the supply of clocks.
(3) Software STOP mode
In this mode, the CPU clock, the internal system clock, and the clock generator are stopped, reducing power
consumption to just the leakage current. In this state, power consumption is minimized.
Setting the PSC register, which is a specific register, transfers the V854 to the software STOP mode.
(a) PLL mode
Setting the register by software transfers the V854 to the software STOP mode. As soon as the oscillator
circuit stops, the clock output of the PLL synthesizer is stopped. After the software STOP mode has been
released, it is necessary to allow for stabilization time of the oscillator and system clock. Moreover, the
lock up or stabilization time of the PLL may also be necessary, depending on the application.
(b) Direct mode
The software STOP mode cannot be used in direct mode.
(4) Clock output inhibit
Output of the system clock from the CLKOUT pin is prohibited.
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CHAPTER 6 CLOCK GENERATOR FUNCTION
User's Manual U11969EJ3V0UM00
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