Bus Hold Procedure; Operation In Power Save Mode - NEC V850E/RS1 User Manual

5.7.2 Bus hold procedure

The bus hold status transition procedure is shown below.
<1>
<2> All bus cycle start requests inhibited
<3> End of current bus cycle
<4> Shift to bus idle status
<5>
<6>
<7>
<8> Bus cycle start request inhibition released
<9> Bus cycle starts

5.7.3 Operation in power save mode

Because the internal system clock is stopped in the software STOP and IDLE modes, the bus hold
status is not entered even if the HLDRQ pin is asserted.
In the HALT mode, the HLDAK pin is asserted as soon as the HLDRQ pin has been asserted, and the
bus hold status is entered. When the HLDRQ pin is later deasserted, the HLDAK pin is also
deasserted, and the bus hold status is cleared.
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Chapter 5 Bus Control Function
Figure 5-8: Bus Hold Status Transition Procedure
¯¯¯¯¯¯¯
HLDRQ = 0 acknowledged
¯¯¯¯¯¯
HLDAK = 0
¯¯¯¯¯¯¯
HLDRQ = 1 acknowledged
¯¯¯¯¯¯
HLDAK = 1
HLDRQ (input)
HLDAK (output)
<1> <2>
User's Manual U16702EE3V2UD00
Normal status
Bus hold status
Normal status
<3><4> <5> <6> <7><8><9>