Clg Oscillation Control Register; Clg Osc3 Control Register - Epson S1C17M12 Technical Manual

CLG Oscillation Control Register

Register name Bit
CLGOSC 15–12 –
11
10
9
8
7–4 –
3
2
1
0
Bits 15–12, 9 Reserved
Bit 11 EXOSCSLPC
Bit 10 OSC3SLPC
Bit 8 IOSCSLPC
These bits control the clock source operations in SLEEP mode.
1 (R/W): Stop clock source in SLEEP mode
0 (R/W): Continue operation state before SLEEP
Each bit corresponds to the clock source as follows:
CLGOSC.EXOSCSLPC bit: EXOSC clock input
CLGOSC.OSC3SLPC bit: OSC3 oscillator circuit
CLGOSC.IOSCSLPC bit:
Bits 7–4, 1 Reserved
Bit 3 EXOSCEN
Bit 2 OSC3EN
Bit 0 IOSCEN
These bits control the clock source operation.
1(R/W): Start oscillating or clock input
0(R/W): Stop oscillating or clock input
Each bit corresponds to the clock source as follows:
CLGOSC.EXOSCEN bit: EXOSC clock input
CLGOSC.OSC3EN bit:
CLGOSC.IOSCEN bit:

CLG OSC3 Control Register

Register name Bit
CLGOSC3 15–12 –
11–10 OSC3FQ[1:0]
9–8 OSC3MD[1:0]
7–6 –
5–4 OSC3INV[1:0]
3
2–0 OSC3WT[2:0]
Bits 15–12 Reserved
Bits 11–10 OSC3FQ[1:0]
These bits set the oscillation frequency of the OSC3 internal oscillator circuit.
S1C17M12/M13 TECHNICAL MANUAL
(Rev. 1.2)
Bit name Initial
0x0
EXOSCSLPC 1
OSC3SLPC 1
– 0
IOSCSLPC 1
0x0
EXOSCEN 0
OSC3EN 0
– 0
IOSCEN 1
IOSC oscillator circuit
OSC3 oscillator circuit
IOSC oscillator circuit
Bit name Initial
0x0
0x1
0x0
0x0
0x3
– 0
0x6
Seiko Epson Corporation
2 POWER SUPPLY, RESET, AND CLOCKS
Reset R/W
– R –
H0 R/W
H0 R/W
– R
H0 R/W
– R
H0 R/W
H0 R/W
– R
H0 R/W
Reset R/W
– R –
H0 R/WP
H0 R/WP
– R
H0 R/WP
– R
H0 R/WP
Remarks
Remarks
2-13