Clg Oscillation Control Register - Epson S1C17M01 Technical Manual

Bits 13–12 WUPDIV[1:0]
These bits select the SYSCLK division ratio for resetting the CLGSCLK.CLKDIV[1:0] bits at wake-up.
This setting is ineffective when the CLGSCLK.WUPMD bit = 0.
Bits 11–10 Reserved
Bits 9–8 WUPSRC[1:0]
These bits select the SYSCLK clock source for resetting the CLGSCLK.CLKSRC[1:0] bits at wake-up.
However, this setting is ineffective when the CLGSCLK.WUPMD bit = 0.
Note: Do not select a clock source that has stopped. When selecting it, set the clock source enable
bit to 1 before executing the slp instruction.
Table 2.6.2 SYSCLK Clock Source and Division Ratio Settings at Wake-up
CLGSCLK.
WUPDIV[1:0] bits
0x3
0x2
0x1
0x0
Bits 7–6 Reserved
Bits 5–4 CLKDIV[1:0]
These bits set the division ratio of the clock source to determine the SYSCLK frequency.
Bits 3–2 Reserved
Bits 1–0 CLKSRC[1:0]
These bits select the SYSCLK clock source.
When a currently stopped clock source is selected, it will automatically start oscillating or clock input.
CLGSCLK.
CLKDIV[1:0] bits
0x3
0x2
0x1
0x0

CLG Oscillation Control Register

Register name Bit
CLGOSC 15–12 –
11
10
9
8
7–4 –
3
2
1
0
Bits 15–12 Reserved
S1C17M01 TECHNICAL MANUAL
(Rev. 1.2)
0x0
IOSCCLK
1/8
1/4
1/2
1/1
Table 2.6.3 SYSCLK Clock Source and Division Ratio Settings
0x0
IOSCCLK
1/8
1/4
1/2
1/1
Bit name Initial
0x0
EXOSCSLPC
–
OSC1SLPC
IOSCSLPC
0x0
EXOSCEN
–
OSC1EN
IOSCEN
Seiko Epson Corporation
2 POWER SUPPLY, RESET, AND CLOCKS
CLGSCLK.WUPSRC[1:0] bits
0x1 0x2
OSC1CLK –
Reserved Reserved
Reserved Reserved
1/2 Reserved
1/1 Reserved
CLGSCLK.CLKSRC[1:0] bits
0x1 0x2
OSC1CLK –
Reserved Reserved
Reserved Reserved
1/2 Reserved
1/1 Reserved
Reset R/W
– R –
1 H0 R/W
1 – R
1 H0 R/W
1 H0 R/W
– R
0 H0 R/W
0 – R
0 H0 R/W
1 H0 R/W
0x3
EXOSCCLK
Reserved
Reserved
Reserved
1/1
0x3
EXOSCCLK
Reserved
Reserved
Reserved
1/1
Remarks
2-13