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2 POWER SUPPLY, RESET, AND CLOCKS
Bits 11–10 Reserved
Bits 9–8
WuPSRC[1:0]
These bits select the SYSCLK clock source for resetting the CLGSCLK.CLKSRC[1:0] bits at wake-up.
When a currently stopped clock source is selected, it will automatically start oscillating or clock input
at wake-up. However, this setting is ineffective when the CLGSCLK.WUPMD bit = 0.
Table 2.
CLGSCLK.
WUPDIV[1:0] bits
0x3
0x2
0x1
0x0
Bits 7–6
Reserved
Bits 5–4
ClKDiV[1:0]
These bits set the division ratio of the clock source to determine the SYSCLK frequency.
Bits 3–2
Reserved
Bits 1–0
ClKSRC[1:0]
These bits select the SYSCLK clock source.
When a currently stopped clock source is selected, it will automatically start oscillating or clock input.
CLGSCLK.
CLKDIV[1:0] bits
0x3
0x2
0x1
0x0
ClG Oscillation Control Register
Register name
Bit
CLGOSC
15–12 –
11
10
9
8
7–4 –
3
2
1
0
Bits 15–12 Reserved
Bit 11
eXOSCSlPC
Bit 10
OSC3aSlPC
Bit 9
OSC1SlPC
Bit 8
OSC3BSlPC
These bits control the clock source operations in SLEEP mode.
1 (R/W): Stop clock source in SLEEP mode
0 (R/W): Continue operation state before SLEEP
2-14
6.2 SYSCLK Clock Source and Division Ratio Settings at Wake-up
0x0
OSC3BCLK
Reserved
Reserved
1/2
1/1
Table 2.
6.3 SYSCLK Clock Source and Division Ratio Settings
0x0
OSC3BCLK
Reserved
Reserved
1/2
1/1
Bit name
Initial
0x0
EXOSCSLPC
OSC3ASLPC
OSC1SLPC
OSC3BSLPC
0x0
EXOSCEN
OSC3AEN
OSC1EN
OSC3BEN
Seiko epson Corporation
CLGSCLK.WUPSRC[1:0] bits
0x1
0x2
–
OSC3ACLK
Reserved
1/8
Reserved
1/4
Reserved
1/2
Reserved
1/1
CLGSCLK.CLKSRC[1:0] bits
0x1
0x2
OSC1CLK
OSC3ACLK
Reserved
1/8
Reserved
1/4
1/2
1/2
1/1
1/1
Reset
R/W
–
R
–
1
H0
R/W
1
H0
R/W
1
H0
R/W
1
H0
R/W
–
R
0
H0
R/W
0
H0
R/W
0
H0
R/W
1
H0
R/W
0x3
EXOSCCLK
Reserved
Reserved
Reserved
1/1
0x3
EXOSCCLK
Reserved
Reserved
Reserved
1/1
Remarks
S1C17F13 TeChniCal Manual
(Rev. 1.0)
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