Input/Output Pins; Clock Sources - Epson S1C17M01 Technical Manual

2 POWER SUPPLY, RESET, AND CLOCKS
• Controls the oscillator and clock input circuits to enable/disable according to the operating mode, RUN or
SLEEP mode.
• Provides a flexible system clock switching function at SLEEP mode cancelation.
- The clock sources to be stopped in SLEEP mode can be selected.
- SYSCLK to be used at SLEEP mode cancelation can be selected from all clock sources.
- The oscillator and clock input circuit on/off state can be maintained or changed at SLEEP mode cancelation.
• Provides the FOUT function to output an internal clock for driving external ICs or for monitoring the internal
state.
Figure 2.3.1.1 shows the CLG configuration.
CLG
OSC1
X'tal1
OSC2
EXOSC
FOUT

2.3.2 Input/Output Pins

Table 2.3.2.1 lists the CLG pins.
Pin name I/O*
OSC1 A
OSC2 A
EXOSC I
FOUT O
If the port is shared with the CLG input/output function and other functions, the CLG function must be assigned to
the port. For more information, refer to the "I/O Ports" chapter.

2.3.3 Clock Sources

IOSC oscillator circuit
The IOSC oscillator circuit features a fast startup and no external parts are required for oscillating. Figure 2.3.3.1
shows the configuration of the IOSC oscillator circuit.
2-4
IOSCEN
IOSC
IOSCCLK
oscillator Divider
circuit
OSC1EN
OSC1
OSC1CLK
oscillator Divider
circuit
EXOSCEN
EXOSC
EXOSCCLK
clock input
circuit
FOUTEN
FOUT
output
circuit
FOUTDIV[2:0]
Figure 2.3.1.1 CLG Configuration
Table 2.3.2.1 List of CLG Pins
Initial status*
– OSC1 oscillator circuit input
– OSC1 oscillator circuit output
I EXOSC clock input
O (L) FOUT clock output
Seiko Epson Corporation
CLKSRC[1:0]
CLKDIV[1:0]
WUPSRC[1:0]
WUPDIV[1:0]
WUPMD
System
Clock
clock
selector
controller
SLEEP, WAKE-UP
Clock
selector
Clock
selector
Function
* Indicates the status when the pin is configured for CLG.
SYSCLK
To CPU and bus
Peripheral circuit 1
CLKSRC[x:0]
CLKDIV[x:0]
Peripheral circuit n
CLKSRC[x:0]
CLKDIV[x:0]
S1C17M01 TECHNICAL MANUAL
(Rev. 1.2)