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14 SYNCHRONOUS SERIAL INTERFACE (SPIA)
14.5.3 Data Reception in Master Mode
A data receiving procedure and operations in master mode are shown below. Figures 14.5.3.1 and 14.5.3.2 show a
timing chart and flowcharts, respectively.
Data receiving procedure
1. Assert the slave select signal by controlling the general-purpose output port (if necessary).
2. Check to see if the SPIA_nINTF.TBEIF bit is set to 1 (transmit buffer empty).
3. Write dummy data (or transmit data) to the SPIA_nTXD register.
4. Wait for a transmit buffer empty interrupt (SPIA_nINTF.TBEIF bit = 1).
5. Write dummy data (or transmit data) to the SPIA_nTXD register.
6. Wait for a receive buffer full interrupt (SPIA_nINTF.RBFIF bit = 1).
7. Read the received data from the SPIA_nRXD register.
8. Repeat Steps 5 to 7 until the end of data reception.
9. Negate the slave select signal by controlling the general-purpose output port (if necessary).
Note: To perform continuous data reception without stopping SPICLKn, Steps 7 and 5 operations must
be completed within the SPICLKn cycles equivalent to "Data bit length - 1" after Step 6.
Data receiving operations
SPIA Ch.n starts data receiving operations simultaneously with data sending operations when transmit data (may
be dummy data if data transmission is not required) is written to the SPIA_nTXD register.
The SPICLKn pin outputs clocks of the number of the bits specified by the SPIA_nMOD.CHLN[3:0] bits. The
transmit data bits are output in sequence from the SDOn pin in sync with these clocks and the receive data bits
input from the SDIn pin are shifted into the shift register.
When the last clock is output from the SPICLKn pin and receive data bits are all shifted into the shift register,
the received data is transferred to the receive data buffer and the SPIA_nINTF.RBFIF bit is set to 1. At the
same time SPIA issues a receive buffer full interrupt request if the SPIA_nINTE.RBFIE bit = 1. After that, the
received data in the receive data buffer can be read through the SPIA_nRXD register.
Note: If data of the number of the bits specified by the SPIA_nMOD.CHLN[3:0] bits is received when
the SPIA_nINTF.RBFIF bit is set to 1, the SPIA_nRXD register is overwritten with the newly re-
ceived data and the previously received data is lost. In this case, the SPIA_nINTF.OEIF bit is set.
SPICLKn
SDOn
SDIn
SPIA_nINTF.TBEIF
SPIA_nINTF.RBFIF
SPIA_nINTF.TENDIF
Data (W) → SPIA_nTXD
Software operations
Figure 14.5.3.1 Example of Data Receiving Operations in Master Mode (SPIA_nMOD.CHLN[3:0] bits = 0x7)
14-8
1 2 3 4 5 6 7 8
SPIA_nRXD → Data (R)
1 (W) → SPIA_nINTF.TENDIF
Seiko Epson Corporation
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
Data (W) → SPIA_nTXD
Data (W) → SPIA_nTXD
SPIA_nRXD → Data (R)
SPIA_nRXD → Data (R)
S1C31D41 TECHNICAL MANUAL
(Rev. 1.1)
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