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Bit 0
UFIF
This bit indicates the T16 Ch.n underflow interrupt cause occurrence status.
1 (R):
Cause of interrupt occurred
0 (R):
No cause of interrupt occurred
1 (W):
Clear flag
0 (W):
Ineffective
T16 Ch.n Interrupt Enable Register
Register name
Bit
T16_nINTE
15–8 –
7–1 –
0
Bits 15–1 Reserved
Bit 0
UFIE
This bit enables T16 Ch.n underflow interrupts.
1 (R/W): Enable interrupts
0 (R/W): Disable interrupts
Note: To prevent generating unnecessary interrupts, the corresponding interrupt flag should be
cleared before enabling interrupts.
S1C17M01 TECHNICAL MANUAL
(Rev. 1.2)
Bit name
Initial
0x00
0x00
UFIE
0
Seiko Epson Corporation
Reset
R/W
–
R
–
–
R
H0
R/W
10 16-BIT TIMERS (T16)
Remarks
10-7
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