Sdq To Sdqs Mapping; Table 27. Sdq/Sdm To Sdqs Mapping - Intel 855GM Design Manual

System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration
Length matching is not required from the SO-DIMM1 to the parallel termination resistors. Figure 38 on
the following page depicts the length matching requirements between the SDQ, SDM, and SDQS
signals within a byte lane. Byte lane mapping is defined in Table 27 below.
6.3.4.4.

SDQ to SDQS Mapping

Table 27 below defines the mapping between the nine byte lanes, nine mask bits, and the nine SDQS
signals, as required to do the required length matching.

Table 27. SDQ/SDM to SDQS Mapping

Signal
SDQ[7:0]
SDQ[15:8]
SDQ[23:16]
SDQ[31:24]
SDQ[39:32]
SDQ[56:40]
SDQ[55:48]
SDQ[63:56]
SDQ[71:64]
88
Mask Relative To
SDM[0] SDQS[0]
SDM[1] SDQS[1]
SDM[2] SDQS[2]
SDM[3] SDQS[3]
SDM[4] SDQS[4]
SDM[5] SDQS[5]
SDM[6] SDQS[6]
SDM[7] SDQS[7]
SDM[8] SDQS[8]
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Intel 855GM/855GME Chipset Platform Design Guide
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