Setting Overflow Time Of Watchdog Timer - NEC 78K0R/KE3 User Manual

Cautions 4. The operation of the watchdog timer in the HALT and STOP modes differs as follows
depending on the set value of bit 0 (WDSTBYON) of the option byte (000C0H).
In HALT mode
In STOP mode
If WDSTBYON = 0, the watchdog timer resumes counting after the HALT or STOP mode is
released. At this time, the counter is cleared to 0 and counting starts.
When operating with the X1 oscillation clock after releasing the STOP mode, the CPU starts
operating after the oscillation stabilization time has elapsed.
Therefore, if the period between the STOP mode release and the watchdog timer overflow is
short, an overflow occurs during the oscillation stabilization time, causing a reset.
Consequently, set the overflow time in consideration of the oscillation stabilization time
when operating with the X1 oscillation clock and when the watchdog timer is to be cleared
after the STOP mode release by an interval interrupt.
5. The watchdog timer continues its operation during self-programming of the flash memory
and EEPROM emulation. During processing, the interrupt acknowledge time is delayed. Set
the overflow time and window size taking this delay into consideration.

8.4.2 Setting overflow time of watchdog timer

Set the overflow time of the watchdog timer by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (000C0H).
If an overflow occurs, an internal reset signal is generated. The present count is cleared and the watchdog timer
starts counting again by writing "ACH" to WDTE during the window open period before the overflow time.
The following overflow time is set.
WDCS2
0
0
0
0
1
1
1
1
Caution The watchdog timer continues its operation during self-programming of the flash memory and
EEPROM emulation. During processing, the interrupt acknowledge time is delayed. Set the
overflow time and window size taking this delay into consideration.
Remarks 1. f : Internal low-speed oscillation clock frequency
IL
2. ( ): f = 264 kHz (MAX.)
IL
CHAPTER 8 WATCHDOG TIMER
WDSTBYON = 0
Watchdog timer operation stops.
Table 8-3. Setting of Overflow Time of Watchdog Timer
WDCS1 WDCS0
10
0 0 2
11
0 1 2
12
1 0 2
13
1 1 2
15
0 0 2
17
0 1 2
18
1 0 2
20
1 1 2
User's Manual U17854EJ9V0UD
Watchdog timer operation continues.
Overflow Time of Watchdog Timer
/f (3.88 ms)
IL
/f (7.76 ms)
IL
/f (15.52 ms)
IL
/f (31.03 ms)
IL
/f (124.12 ms)
IL
/f (496.48 ms)
IL
/f (992.97 ms)
IL
/f (3971.88 ms)
IL
WDSTBYON = 1
293