Registers To Control 8-Bit Timer/Event Counters 50 And 51 - NEC mPD780024AS Series Preliminary User's Manual

7.3 Registers to Control 8-Bit Timer/Event Counters 50 and 51

The following three types of registers are used to control 8-bit timer/event counters 50 and 51.
• Timer clock select register 5n (TCL5n)
• 8-bit timer mode control register 5n (TMC5n)
• Port mode register 7 (PM7)
n = 0, 1
(1) Timer clock select register 5n (TCL5n: n = 0, 1)
This register sets count clocks of 8-bit timer/event counter 5n and the valid edge of TI50, TI51 input.
TCL5n is set by an 8-bit memory manipulation instruction.
RESET input sets TCL5n to 00H.
Figure 7-3. Format of Timer Clock Select Register 50 (TCL50)
Address: FF71H After reset: 00H
Symbol 7
TCL50 0
TCL502
0
0
0
0
1
1
1
1
Cautions 1. When rewriting TCL50 to other data, stop the timer operation beforehand.
2. Be sure to set bits 3 to 7 to 0.
Remarks 1. When cascade connection is used, only the settings of TCL502 to TCL00 are valid.
2. f : Main system clock oscillation frequency
X
3. Figures in parentheses are for operation with f
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51
R/W
6 5
0 0
TCL501 TCL500
0 0 TI50 falling edge
0 1 TI50 rising edge
1 0 f (8.38 MHz)
X
2
1 1 f /2
X
4
0 0 f /2
X
6
0 1 f /2
X
8
1 0 f /2
X
10
1 1 f /2
X
Preliminary User's Manual U16035EJ1V0UM
4 3 2
0 0 TCL502
Count clock selection
(2.09 MHz)
(523 kHz)
(131 kHz)
(32.7 kHz)
(8.18 kHz)
= 8.38 MHz
X
1 0
TCL501 TCL500
135