Table of Contents
Advertisement
7.3 Registers Controlling 8-Bit Timer/Event Counter 50
The following four registers are used to control 8-bit timer/event counter 50.
• Timer four selection register 50 (TCL50)
• 8-bit timer mode control register 50 (TMC50)
• Port mode register 1 (PM1)
• Port register 1 (P1)
(1) Timer clock selection register 50 (TCL50)
This register sets the count clock of 8-bit timer/event counter 50 and the valid edge of the TI50 pin input.
TCL50 can be set by an 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 7-4. Format of Timer Clock Selection Register 50 (TCL50)
Address: FF6AH
After reset: 00H
Symbol
7
TCL50
0
TCL502
0
0
0
0
1
1
1
1
Note Be sure to set the count clock so that the following condition is satisfied.
• V
= 4.0 to 5.5 V: Count clock ≤ 10 MHz
DD
• V
= 3.3 to 4.0 V: Count clock ≤ 8.38 MHz
DD
• V
= 2.7 to 3.3 V: Count clock ≤ 5 MHz
DD
Cautions 1. When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the clock of the
Ring-OSC oscillator is divided and supplied as the count clock. If the count clock is the
Ring-OSC clock, the operation of 8-bit timer/event counter 50 is not guaranteed.
2. When rewriting TCL50 to other than the same data, stop the timer operation beforehand.
3. Be sure to set bits 3 to 7 to 0.
Remarks 1. f
: High-speed system clock oscillation frequency
X
2. Figures in parentheses apply to operation at f
CHAPTER 7 8-BIT TIMER/EVENT COUNTER 50
R/W
6
5
0
0
TCL501
TCL500
0
0
TI50 pin falling edge
0
1
TI50 pin rising edge
1
0
f
(10 MHz)
X
1
1
f
/2 (5 MHz)
X
2
0
0
f
/2
X
6
0
1
f
/2
X
8
1
0
f
/2
X
13
1
1
f
/2
X
Preliminary User's Manual U16846EJ1V0UD
4
3
2
0
0
TCL502
Count clock selection
(2.5 MHz)
(156.25 kHz)
(39.06 kHz)
(1.22 kHz)
= 10 MHz.
X
1
0
TCL501
TCL500
Note
145
Advertisement
Table of Contents
