Registers Controlling 8-Bit Timer/Event Counters 50 And 51 - NEC 78K0 User Manual

8.3

Registers Controlling 8-Bit Timer/Event Counters 50 and 51

The following four registers are used to control 8-bit timer/event counters 50 and 51.
• Timer clock selection register 5n (TCL5n)
• 8-bit timer mode control register 5n (TMC5n)
• Port mode register 1 (PM1) or port mode register 3 (PM3)
• Port register 1 (P1) or port register 3 (P3)
(1) Timer clock selection register 5n (TCL5n)
This register sets the count clock of 8-bit timer/event counter 5n and the valid edge of TI5n input.
TCL5n can be set by an 8-bit memory manipulation instruction.
RESET input clears TCL5n to 00H.
Remark n = 0, 1
Figure 8-5. Format of Timer Clock Selection Register 50 (TCL50)
Address: FF6AH After reset: 00H
Symbol 7
TCL50 0
TCL502
0
0
0
0
1
1
1
1
Cautions 1. When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the clock of the
Ring-OSC oscillator is divided and supplied as the count clock. If the count clock is the
Ring-OSC clock, the operation of 8-bit timer/event counter 50 is not guaranteed.
2. When rewriting TCL50 to other data, stop the timer operation beforehand.
3. Be sure to clear bits 3 to 7 to 0.
Remarks 1. f : X1 input clock oscillation frequency
X
2. Figures in parentheses apply to operation at f
216
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51
R/W
6 5
0 0
TCL501 TCL500
0 0 TI50 falling edge
0 1 TI50 rising edge
1 0 f (10 MHz)
X
1 1 f /2 (5 MHz)
X
2
0 0 f /2
X
6
0 1 f /2
X
8
1 0 f /2
X
13
1 1 f /2
X
User's Manual U15947EJ2V0UD
4 3 2
0 0 TCL502
Count clock selection
*
(2.5 MHz)
(156.25 kHz)
(39.06 kHz)
(1.22 kHz)
= 10 MHz.
X
1 0
TCL501 TCL500