Figure 4. Clock Tree - ST STM32C0 Series Getting Started

• RTC, with these clock sources to select from:
– LSE
– LSI
– HSE clock divided by 32
The functionality in Stop mode (including wake-up) is supported only when the clock is LSI or LSE.
• IWDG, always clocked with LSI clock.
• SysTick (Cortex
– HCLK (AHB clock)
– HCLK clock divided by 8
The selection is done through SysTick control and status register.
HCLK is used as Cortex
PM0223.
LSCO
OSC32_OUT
OSC32_IN
MCO
/ 1,2,...,128
(2)
MCO2
/ 1,2,...,128
OSC_OUT
OSC_IN
I2S_CKIN
BOLD: clock origin
(1) TIMPCLK is running at PCLK frequency if the APB prescaler division factor is set to 1, or at twice the PCLK
frequency otherwise
AN5673 - Rev 2
®
core system timer), with these clock sources to select from:
®
-M0+ free-running clock (FCLK). For more details, refer to the programming manual
LSI
LSI RC
32 kHz
LSI
LSE
LSE OSC
32.768 kHz
LSE
Clock
detector
LSE
LSI
SYSCLK
HSE
HSI48
HSE OSC
4-48 MHz
HSE
Clock
detector
HSI48
HSI48 RC
/1,2,4,...,128
48 MHz
/1,2,3,...,8
Figure 4. Clock tree
LSI
RTCCLK
LSE
HSE
/32
HCLK
AHB PRESC
/ 1,2,4,..,512
LSE
LSI
SYSCLK
HSE
HSISYS
HSISYS
HSIKER
AN5673
to IWDG
to RTC
to PWR
to AHB bus, core, memory and DMA
FCLK Cortex free-running clock
to Cortex system timer
HCLK8
/ 8
APB
PCLK
to APB peripherals
PRESC
/ 1,2,4,8,16
to TIM1/3/
14/16/17
(1)
x1, x2
TIMPCLK
PCLK
LSE
to USART1
HSIKER
SYSCLK
PCLK
HSIKER to I2C1
SYSCLK
async clock
SYSCLK
to ADC
HSIKER
SYSCLK
to I2S1
HSIKER
I2S_CKIN
Clocks
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