Figure 2. Clock Tree - ST STM32L15 QC Series Datasheet

Functional overview
Standby supplied voltage domain
LSE OSC
@V33
MSI RC
level shifters
@V
@V33
level shifters
@V
@V33
level shifters
@V
@V33
1 MHz clock
22/134
enable
Watchdog
LSI RC LSI tempo
LSE tempo
LS
@V
DDCORE
1 MHz
DDCORE
/ 2,4,8,16
HSI RC
DDCORE
HSE
OSC
DDCORE
LS
detector
HSE present or not
LS
CK_USB48
ck_usb = Vco / 2 (Vco must be at 96 MH
CK_TIMTGO
apb1 periphen and (not deepsleep)
CK_APB1
apb2 periphen and (not deepsleep)
CK_APB2
STM32L151xC/C-A STM32L152xC/C-A

Figure 2. Clock tree

Watchdog
LS
RTC enable
Radio Sleep Timer enable
LS LS LS
ck_lsi
ck_lse
ck_msi
ck_hsi
ck_hse
ck_pll
@V33
PLL
ck_pllin
X 3,4,6,8,12
16,24,32,48
/ 2, 3, 4
level shifters
@V
DDCORE
usben and (not deepsleep)
z)
timer9en and (not deepsleep)
DS10262 Rev 8
RTC
Radio Sleep Timer
LCD enable
ADC enable
MCO
/ 1,2,4,8,16
not deepsleep
not deepsleep
not (sleep or
deepsleep
System
not (sleep or
clock
deepsleep)
AHB
prescaler
/ 1,2,..512
APB1
prescaler prescaler
/ 1,2,4,8,16 / 1,2,4,8,16
Clock
source
control
if (APB1 presc = 1)x1
x2
else
CK_LCD
CK_ADC
CK_PWR
CK_FCLK
CK_CPU
CK_TIMSYS
/ 8
APB2
MS18583V1