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MF297-07a CMOS 4 - BIT SINGLE CHIP MICROCOMPUTER S1C6200/6200A Core CPU Manual...
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No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any...
S1C6200/6200A Core CPU Manual ____________________________________________________ 1 ESCRIPTION 1.1 System Features ... 1 1.2 Instruction Set Features ... 1 1.3 Differences between S1C6200 and S1C6200A ... 1 EMORY AND PERATIONS 2.1 Program Memory (ROM) ... 3 2.1.1 Program counter block ... 4 2.1.2 Flags ...
ESCRIPTION The S1C6200/6200A is the Core CPU of the S1C62 Family of CMOS 4-bit single-chip microcomput- ers. The CPU features a highly-integrated architecture. Memory-mapped peripheral circuits can include RAM, ROM, I/O ports, interrupt controllers, timers and LCD drivers, depending upon the application.
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XHL (8) Stack Pointer (8) 12-bit data bus Fig. 1.1 Block diagram EPSON XP (4) YP (4) Oscillator Interrupt Timing Controller Generator A (4) B (4) TEMPB (5) TEMPA (5) I D Z C S1C6200 CORE CPU S1C6200/6200A CORE CPU MANUAL...
EMORY AND A single-chip microcomputer using the S1C6200/6200A Core CPU has four major blocks: the program memory (ROM), the data memory (RAM and I/O), the arithmetic logic unit (ALU) and the timing generator circuit. This section describes each of these blocks in detail.
As only the page data specified by NPP is loaded to PCP when a call instruction is executed, subroutine calls between banks are not possible. Jumps between banks can only be made using JP instructions. S1C6200/6200A CORE CPU MANUAL Table 2.1.3.1 Jump instructions...
The data set by PSET is canceled, and the program jumps to bank 0, page 1, step 9. Bank 0 Page 0 EEE... Bank 0 Page 2 PSET Not effect on destination CALZ of CALZ Fig. 2.1.7.1 The use of the CALZ instruction EPSON S1C6200/6200A CORE CPU MANUAL...
Nesting allows efficient usage of the stack area. As the stack area resides in the data memory, care should be taken to ensure that the stack area is not corrupted by other data. S1C6200/6200A CORE CPU MANUAL CALL with PSET Bank 0...
Fig. 2.2.1 Data memory configuration Register/Pointer Mnemonic Index Register X Index Register Y Stack Pointer Register Fig. 2.2.1.1 The configuration of the index register IX EPSON XHL or YHL (within page) Memory or I/O Register area Size (bits) S1C6200/6200A CORE CPU MANUAL...
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A,Mn B,Mn Mn,A M(n) Mn,B M(n) M(n) M(n) n: 0 to F S1C6200/6200A CORE CPU MANUAL Fig. 2.2.1.2 The configuration of the index register IY Operation Push-down (SP is decremented) Pop-up (SP is incremented) M(n) M(n) where M(n) is the contents of a data memory location within the register area.
D = 1 : Result of Actual D = 0 : Result of decimal operation result hexadecimal operation ALU output EPSON X: Don't care. Subtraction D = 1 : Result of decimal operation ALU output ALU output S1C6200/6200A CORE CPU MANUAL...
The data in A can be paired with that in B for use as an indirect jump address by the JPBA instruction. 2.4 Timing Generator S1C6200/6200A instructions can be divided into three different types depending on the number of clock cycles per instruction: 5, 7 or 12 clock cycles. The more complex the instruction, the more cycles it requires.
2 MEMORY AND OPERATIONS 2.5 Interrupts The S1C6200/6200A can have up to 15 interrupt vectors. When used with peripheral circuits, these allow internal and external interrupts to be processed easily. See Figure 2.5.3.1 through 2.5.3.4. 2.5.1 Interrupt vectors The interrupt vectors are assigned to steps 1 to 15 in page 1 of each bank of the program memory. When an interrupt occurs, the program jumps to the appropriate interrupt vector in the current bank.
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INT1 and INT2 are dummy instructions Branches to the top of the interrupt service routine (*2) Fig. 2.5.3.4 Interrupt timing with PSET EPSON INT1 (*1) INT2 (*1) JP (*2) INT2 (*1) JP (*2) INT2 (*1) JP (*2) S1C6200/6200A CORE CPU MANUAL...
When using the model loaded with the S1C6200 Core CPU, set or reset the D flag in the user's initial routine before using an arithmetic instruction. (refer to the SDF and RDF instructions.) S1C6200/6200A CORE CPU MANUAL Table 2.5.4.1 Reset value Bit length Table 2.5.4.2 D (decimal) flag initial setting...
3 INSTRUCTION SET NSTRUCTION This chapter describes the entire instruction set of the S1C6200/6200A Core CPU. A subset is allocated to each device within the S1C62 Family according to the configuration of the device. Therefore not all instructions are available in every device. The relevant information is in the technical manual for each device.
XP r, XH r, XL r, YP r, YH r, YL XH, i XL, i YH, i YL, i S1C6200/6200A CORE CPU MANUAL Operation Code Flag Clock I D Z C EPSON 3 INSTRUCTION SET Operation p4, NPP p3~p0...
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ACPX MX, r ACPY MY, r SCPX MX, r SCPY MY, r S1C6200/6200A CORE CPU MANUAL Operation Code Flag Clock I D Z C EPSON 3 INSTRUCTION SET Operation M(SP), SP SP+1 M(SP), SP...
NPP, PCS s7~s0 if C=1 NBP, PCP NPP, PCS s7~s0 if C=0 NBP, PCP NPP, PCS s7~s0 if Z=0 NBP, PCP NPP, PCS s7~s0 NBP, PCP NPP, PCS s7~s0 if Z=1 e3~e0, M(X+1) e7~e4, X S1C6200/6200A CORE CPU MANUAL PCSL+1 PCSL+1...
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Y, e LDPX MX, i r, q LDPY MY, i r, q NOP5 NOP7 r, i r, q S1C6200/6200A CORE CPU MANUAL Flag Clock I D Z C M(n3~n0) M(n3~n0) i3~i0 M(X) q, X M(Y) q, Y No operation (5 clock cycles)
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X M(SP), PCSH M(SP+1), PCP M(SP+2) SP+3, PC PC+1 d2, d2 d1, d1 d0, d0 C, C C, d2 d3, d1 d2, d0 d1, C F i3~i0 M(X)-r-C, X M(Y)-r-C, Y 1 (Decimal Adjuster ON) FVi3~i0 S1C6200/6200A CORE CPU MANUAL...
D0F to D3F D40 to D7F r, i D80 to DBF r, i DC0 to DFF r, i E00 to E3F r, i S1C6200/6200A CORE CPU MANUAL Flag Clock I D Z C EPSON 3 INSTRUCTION SET Operation NBP, PCP NPP, PCS...
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Y M(X) M(X)+r+C, X M(Y) M(Y)+r+C, Y M(X) M(X)-r-C, X M(Y) M(Y)-r-C, Y FVi3~i0 1 (Decimal Adjuster ON) 1 (Enables Interrupt) F i3~i0 0 (Disables Interrupt) 0 (Decimal Adjuster OFF) M(n3~n0) M(n3~n0)+1 M(n3~n0) M(n3~n0)-1 M(n3~n0) S1C6200/6200A CORE CPU MANUAL...
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SPH, r FE4 to FE7 r, SPH JPBA FF0 to FF3 SPL, r FF4 to FF7 r, SPL HALT NOP5 NOP7 S1C6200/6200A CORE CPU MANUAL Flag Clock I D Z C EPSON 3 INSTRUCTION SET Operation M(n3~n0) M(n3~n0) M(n3~n0) SP-1, M(SP)
POP F instruction. When an interrupt is generated, the I flag is automatically reset. It is not automatically set at the end of the interrupt service routine. Table 3.2.1 Values of r and q r1 or q1 r0 or q0 EPSON S1C6200/6200A CORE CPU MANUAL...
Instructions are divided into six types according to the size of the operand. Op-code (II) Op-code (III) Op-code (IV) Op-code Op-code (VI) 3.5 Instruction Descriptions This section describes S1C6200/6200A instructions in alphabetical order. S1C6200/6200A CORE CPU MANUAL 8-bit operand 6-bit operand 5-bit operand 4-bit operand 2-bit operand Op-code EPSON 3 INSTRUCTION SET...
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Adds the carry bit and the contents of the q-register to the r-register. Example: A register B register Memory (MX) Memory (MY) C flag Z flag S1C6200/6200A CORE CPU MANUAL to i ADC MX,3 0100 1000 1001 1001 ADC MY,A...
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Adds the carry bit and immediate data i to XL, the four low-order bits of XHL. Example: XL register C flag Z flag to i ADC XH,2 ADC XH,4 1001 1100 to i ADC XL,3 ADC XL,0EH 0000 0100 EPSON A00H to A0FH 0000 A10H to A1FH 0010 S1C6200/6200A CORE CPU MANUAL...
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Not affected Description: Adds the carry bit and immediate data i to YL, the four low-order bits of YHL. Example: YL register C flag Z flag S1C6200/6200A CORE CPU MANUAL to i ADC YH,3 ADC YH,6 1010 1110 to i...
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Z flag to i ADD A,5 1010 1111 0110 0110 ADD A,MY 0010 1111 0100 0100 0111 0111 1101 1101 EPSON C00H to C3FH ADD MY,2 1111 1000 A80H to A8FH ADD MX,B 1111 0100 1011 1101 S1C6200/6200A CORE CPU MANUAL...
Performs a logical AND operation between the contents of the q-register and the contents of the r-register. The result is stored in the r-register. Example: A register B register Memory (MX) Memory (MY) C flag Z flag S1C6200/6200A CORE CPU MANUAL to i AND A,5 0110 0100 1000 1000 AND MX,A 0100...
3. When Z = 0 and C = 1 then q > r Example: A register B register Memory (MY) C flag Z flag S1C6200/6200A CORE CPU MANUAL to i ; otherwise, reset. to i ; otherwise, reset. CP A,4 CP MX,7...
2. When Z = 1 and C = 0 then i = YL Example: 3. When Z = 0 and C = 1 then i > YL Example: YL register C flag Z flag S1C6200/6200A CORE CPU MANUAL to i to i ; otherwise, reset. to i ; otherwise, reset. CP YH,0AH...
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Z flag to n ) - 1 DEC M0 DEC M2 1001 1000 0000 0000 0001 0001 DEC SP 1011 0001 1011 0000 EPSON F70H to F7FH DEC M0FH 1000 1000 1111 1111 0001 0000 FCBH S1C6200/6200A CORE CPU MANUAL...
Clock Cycles: Flag: C – Not affected Z – Not affected D – Not affected I – Description: Enables all interrupts. Example: C flag Z flag D flag I flag S1C6200/6200A CORE CPU MANUAL F57H F48H EPSON 3 INSTRUCTION SET...
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FAN A,B FAN MX,B 1000 1000 1010 1010 0101 0101 1110 1110 EPSON D80H to DBFH FAN B,2 1000 1000 0100 0100 1000 1000 F10H to F1FH FAN A,MY 1000 1000 1010 1010 0101 0101 1110 1110 S1C6200/6200A CORE CPU MANUAL...
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Not affected Description: The contents of the data memory location addressed by Mn is incremented by 1. Example: Memory (01H) Memory (03H) Memory (0DH) C flag Z flag S1C6200/6200A CORE CPU MANUAL Instruction State HALT 0001 HALT 0001 0001 to n...
Increments the contents of register X by 1. This operation does not affect the flags. Example: X register C flag Z flag FDBH INC SP 1110 1111 1111 0000 EE0H INC X 1111 1110 1111 1111 EPSON S1C6200/6200A CORE CPU MANUAL...
The b-register contains the four high-order bits of the address and the a- register contains the four low-order bits of the address. Example: A register B register S1C6200/6200A CORE CPU MANUAL INC Y 1011 0111 1011 1000 NBP, PCP...
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1000 1111 1001 0000 EPSON if C = 1 200H to 2FFH JP C,10H 0010 0110 0110 0110 0011 1110 0001 0000 0000 0000 if C = 0 300H to 3FFH JP NC,10H 0001 0001 0001 0000 S1C6200/6200A CORE CPU MANUAL...
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Z – Not affected D – Not affected I – Not affected Description: Unconditional jump to the destination address specified by the 8-bit operand. Example: S1C6200/6200A CORE CPU MANUAL NBP, PCP NPP, PCS to s JP NZ,10H 0000 0000 0000 0000...
I – Not affected Description: Loads the contents of the data memory location addressed by Mn into the B- register. Example: B register Memory (07H) Memory (08H) S1C6200/6200A CORE CPU MANUAL to n LD A,M5 0100 1111 1111 1111 0100 0100...
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Loads the contents of the q-register into the r-register. X is incremented by 1. Incrementing X does not affect the flags. Example: X register A register B register Memory (MY) S1C6200/6200A CORE CPU MANUAL to i X + 1 LDPX MX,7 LDPX MX,0AH 1000 0011 1000 0100...
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D – Not affected I – Not affected Description: The contents of the q-register are loaded into the r-register. Example: A register B register Memory (MY) S1C6200/6200A CORE CPU MANUAL LD A,6 0101 0110 1001 1001 LD A,B 0010 0000 0000...
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Not affected I – Not affected Description: Loads the four low-order bits of register X into the r-register. Example: XL register A register Memory (MY) S1C6200/6200A CORE CPU MANUAL EA4H to EA7H LD B,XH LD MX,XH 1010 1010 1010 0010 1010...
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I – Not affected Description: Loads the 4-bit page part of index register IY into the r-register. Example: YP register B register Memory (MY) S1C6200/6200A CORE CPU MANUAL EB8H to EBBH LD B,YL LD MX,YL 0000 0000 0000 0110 0000...
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I – Not affected Description: Loads the contents of the r-register into the four high-order bits of register X. Example: XH register A register Memory (MY) S1C6200/6200A CORE CPU MANUAL to e , XL to e LD X,6FH 0000 0110 1011...
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I – Not affected Description: Loads the contents of the r-register into the four high-order bits of register Y. Example: YH register B register Memory (MX) S1C6200/6200A CORE CPU MANUAL to e , YL to e LD Y,E1H 0001 1110 1100...
D – Not affected I – Not affected Description: Increments the program counter by 1. Has no other effect for 7 clock cycles. Example: S1C6200/6200A CORE CPU MANUAL 1 0 1 1 FFBH NOP5 0011 0011 0001 0011 0001 0100...
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Memory (MX) Z flag 1 1 1 1 NOT A 1001 0110 1111 1111 to i OR B,5 0100 0101 0011 0011 EPSON D0FH to D3FH NOT MY 0110 0000 CC0H to CFFH OR MX,0BH 0101 0111 S1C6200/6200A CORE CPU MANUAL...
Description: Replaces the flags (F) with the contents of the data memory location addressed by the stack pointer. SP is incremented by 1. Example: Memory (C0H) Flags (I,D,Z,C) S1C6200/6200A CORE CPU MANUAL OR MY,0 0011 0011 0000 0000 SP + 1...
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SP + 1 0 0 r FD0H to FD3H M(SP) = POP B 1001 1001 0101 1001 SP + 1 0 1 0 1 FD5H M(SP) = POP XH 0110 0110 0010 0110 EPSON = r-register = XH S1C6200/6200A CORE CPU MANUAL...
Loads the contents of the data memory location addressed by the stack pointer into XP, the 4-bit page part of IX. SP is incremented by 1. Example: Memory (B4H) XP register S1C6200/6200A CORE CPU MANUAL SP + 1 0 1 1 0 FD6H M(SP) =...
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Loads the most-significant bit of the 5-bit immediate data p to the new bank pointer (NBP) and the four low-order bits to the new page pointer (NPP). Example: S1C6200/6200A CORE CPU MANUAL SP + 1 0 1 1 1 POP YP...
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A register 1 0 1 0 FCAH M(SP) = PUSH F 0100 0001 0001 0001 0 0 r FC0H to FC3H PUSH A M(SP) = 1000 0010 0010 0010 EPSON flag flag flag flag = r-register S1C6200/6200A CORE CPU MANUAL...
Decrements the stack pointer by 1 and loads the contents of XL, the four low-order bits of XHL, into the data memory location addressed by SP. Example: Memory (CFH) XL register S1C6200/6200A CORE CPU MANUAL 0 1 0 1 FC5H M(SP) = PUSH XH...
Decrements the stack pointer by 1 and loads the contents of YP, the page part of IY, into the data memory location addressed by SP. Example: Memory (BFH) YP register S1C6200/6200A CORE CPU MANUAL 1 0 0 1 FC9H M(SP) = PUSH YL...
Example: A register D flag C flag Z flag 1 1 1 0 F5EH ADD A,4 1101 0001 0001 1 0 1 1 F5BH ADD A,8 LD A,6 0110 0100 0100 EPSON ADD A,8 0110 1110 S1C6200/6200A CORE CPU MANUAL...
RET command. X is incremented by 2. Example: Example: Memory (SP) Memory (SP+1) Memory (SP+2) X register Memory (2AH) Memory (2BH) S1C6200/6200A CORE CPU MANUAL M(SP), PCSH M(SP+1), PCP 1 1 1 1 1101 0010 1000 1101 0010 1101 1101...
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1 1 1 0 RETS 0110 0000 1001 0000 0000 0111 0110 0110 0000 0000 0000 0000 C, C r-register RLC A 0011 0111 EPSON M(SP+2), SP SP + 3, PC FDEH AF0H to AFFH r-register S1C6200/6200A CORE CPU MANUAL PC + 1...
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Reset if i Description: Performs a logical AND operation between immediate data i and the contents of the flags. The result is stored in each respective flag. Example: Flags (I,D,Z,C) S1C6200/6200A CORE CPU MANUAL 1 1 r r-register RRC MY 1010 1101 to i is zero;...
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Subtracts the carry flag and immediate data i from the r-register. Example: A register Memory (MY) C flag Z flag 1 1 0 1 ADD A,3 1101 0000 to i SBC A,9 SBC MY,0DH 1000 1111 1110 1110 EPSON F5DH 0000 D40H to D7FH 1111 0000 S1C6200/6200A CORE CPU MANUAL...
C – Z – Not affected D – Not affected I – Not affected Description: Sets the C (carry) flag. Example: C flag S1C6200/6200A CORE CPU MANUAL AB0H to ABFH SBC A,B SBC MY,MX 1110 1011 1011 0010 0010 0010 1001...
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0101 0000 0101 0001 0110 0100 0010 0010 M(Y) - r - C, Y Y + 1 1 1 r SCPY MY,A 1111 1111 0000 0000 0111 0100 0010 0010 EPSON F38H to F3BH F3CH to F3FH S1C6200/6200A CORE CPU MANUAL...
Performs a logical OR operation between immediate data i and the contents of the flags. The results are stored in each respective flag. Example: Flags (C,Z,D,I) S1C6200/6200A CORE CPU MANUAL 0 1 0 0 to i is 1; otherwise, not affected.
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B register C flag Z flag 1 0 0 1 FF9H Instruction State 0100 0011 0000 0100 0011 0001 SLEEP NOP5 0001 0000 0001 AA0H to AAFH SUB A,B 1100 1001 0011 0011 EPSON I flag S1C6200/6200A CORE CPU MANUAL...
Performs an exclusive-OR operation between immediate data i and the contents of the r-register. The result is stored in the r-register. Example: A register Memory (MX) Z flag S1C6200/6200A CORE CPU MANUAL 0 0 1 0 to i XOR A,12 0110 1010...
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Operation: OP-Code: Type: Clock Cycles: Flag: C – Z – D – I – Description: Example: XOR A,MY 0100 1100 1111 1111 0111 0111 1000 1000 EPSON AE0H to AEFH XOR MX,B 1100 1111 1000 1000 S1C6200/6200A CORE CPU MANUAL...
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Logical AND Clock Cycles: ... Logical OR Flag: C – ... Exclusive-OR Z – ... Reset flag D – ... Set flag I – ... Set/reset flag Description: ... Decimal addition/subtraction Example: S1C6200/6200A CORE CPU MANUAL EPSON 3 INSTRUCTION SET...
12.5 to 24.5 13 to 25 12.5 to 19.5 13 to 20 12.5 to 17.5 13 to 18 14 to 15 14 to 15 12.5 to 24.5 13 to 25 12.5 to 22.5 13 to 23 S1C6200/6200A CORE CPU MANUAL...
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Fetch Clock Status Instruction PSET Interrupt processing: Status: Fetch Fig. A2.2.1 Timing chart of S1C6200A interrupt S1C6200/6200A CORE CPU MANUAL APPENDIX A. S1C6200A (ADVANCED S1C6200) CORE CPU 12-clock Instrruction Interrupt Interrupt processing: 12-clock instruction 7-clock instruction 5-clock instruction Execute Note:...
Particularly when there are multiple interrupt factor flags in the same address, extra caution is required. S1C6200A Possible Fetch Execute Execute next instruction CPU Core S1C6200A Possible EPSON S1C6200 Not possible Fetch Execute Fetch "1" is written to the interrupt mask register INT1(interrupt processing) S1C6200 Not possible S1C6200/6200A CORE CPU MANUAL...
JP NC,s JP NZ,s JP s JP Z,s S1C6200/6200A CORE CPU MANUAL NDEX Add with carry r-register to M(Y), increment Y by 1 ... 28 Add with carry immediate data i to r-register ... 29 Add with carry q-register to r-register ... 29 Add with carry immediate data i to XH ...
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Pop stack data into XP ... 65 Pop stack data into YH ... 66 Pop stack data into YL ... 66 Pop stack data into YP ... 67 Page set ... 67 Push flag onto stack ... 68 EPSON S1C6200/6200A CORE CPU MANUAL...