Page 1 MF1110 - 03 CMOS 4 - BIT SINGLE CHIP MICROCOMPUTER S1C63466 Technical Manual S1C63466 Technical Hardware...
Page 2 No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any...
Page 3 Revisions and Additions for this manual Chapter Section Page Item Contents OSC1 crystal oscillation circuit The table was revised. Appendix Appendix The Appendix was added.
Page 5 The information of the product number change Starting April 1, 2001, the product number has been changed as listed below. Please use the new product number when you place an order. For further information, please contact Epson sales representative. Configuration of product number...
Page 7 4.4 Input Ports (K00–K03 and K10–K13) ............29 4.4.1 Configuration of input ports ..............29 4.4.2 Interrupt function ..................29 4.4.3 Mask option ....................30 4.4.4 I/O memory of input ports ................. 31 4.4.5 Programming notes ................... 33 EPSON S1C63466 TECHNICAL MANUAL...
Page 8 4.11.4 Data input/output and interrupt function ..........79 4.11.5 I/O memory of serial interface ..............82 4.11.6 Programming notes ................. 85 4.12 Sound Generator ..................86 4.12.1 Configuration of sound generator ............86 4.12.2 Mask option ..................... 86 EPSON S1C63466 TECHNICAL MANUAL...
Page 9 OARD FOR A.1 Names and Functions of Each Part ............125 A.2 Connecting to the Target System ..............128 A.3 Usage Precautions ..................130 A.3.1 Operational precautions ................130 A.3.2 Differences with the actual IC ..............130 EPSON S1C63466 TECHNICAL MANUAL...
Page 11 CHAPTER UTLINE The S1C63466 is a microcomputer which has a high-performance 4-bit CPU S1C63000 as the core CPU, ROM (16,384 words × 13 bits), RAM (1,792 words × 4 bits), serial interface, watchdog timer, pro- grammable timer, time base counters (2 systems), SVD circuit, a dot-matrix LCD driver that can drive a maximum 60 segments ×...
Page 12 LCD Driver Timer/Counter 60 SEG × 17 COM SEG0–59 K00–K03 K10–K13 Input Port – TEST CA–CF Power Controller Serial Interface P00–P03 I/O Port P10–P13 P20–P23 R00–R03 Sound Output Port R10–R13 Generator R20–R23 Fig. 1.2.1 Block diagram EPSON S1C63466 TECHNICAL MANUAL...
Page 13 RESET SEG50 SEG17 TEST SEG49 SEG16 SEG48 SEG15 N.C. N.C. N.C. SEG14 N.C. N.C. N.C. N.C. N.C. : No Connection Fig. 1.3.1 Pin layout diagram Note: The pin layout diagram of the both package is same. EPSON S1C63466 TECHNICAL MANUAL...
Page 14 SEG51 SEG18 SEG50 N.C. : No Connection Fig. 1.3.2 Pin layout diagram Note: This package does not have the K12 terminal. For the K12 mask option, "With pull-up resistor" should be chosen when using this package. EPSON S1C63466 TECHNICAL MANUAL...
Page 15 (1/8, 1/16, 1/17 duty can be selected by software) COM15, COM16 93,94 – SEG0–SEG59 14–1,143–110,106–95 50–1,128–119 LCD segment output pin Sound output pin SVD external voltage input pin RESET Initial reset input pin TEST Testing input pin EPSON S1C63466 TECHNICAL MANUAL...
Page 16 The function option generator winfog, that has been prepared as the development software tool of S1C63466, is used for this selection. Mask pattern of the IC is finally generated based on the data created by the winfog. Refer to the "S5U1C63000A Manual"...
Page 17 Refer to Section 4.3.3, "OSC3 oscillation circuit", for details. <Mask option list> The following is the option list for the S1C63466. Multiple selections are available in each option item as indicated in the option list. Refer to Chapter 4, "Peripheral Circuits and Operation", to select the specifica- tions that meet the application system.
Page 18 9. LCD DRIVING POWER 1. Internal 2. External 10. SERIAL PORT INTERFACE POLARITY 1. Positive 2. Negative 11. SVD EXTERNAL VOLTAGE DETECTION 1. Not Use 2. Use 12. SOUND GENERATOR POLARITY FOR OUTPUT 1. Positive 2. Negative EPSON S1C63466 TECHNICAL MANUAL...
Page 19 The S1C63466 operates by applying a single power supply within the above range between V and V The S1C63466 itself generates the voltage necessary for all the internal circuits by the built-in power supply circuits shown in Table 2.1.2. Table 2.1.2 Power supply circuits...
Page 20 The S1C63466 is designed with twin clock specification; it has two types of oscillation circuits OSC1 and OSC3 built-in. Use OSC1 clock for normal operation, and switch it to OSC3 by the software when high- speed operation is necessary.
Page 21 CHAPTER 2: POWER SUPPLY AND INITIAL RESET 2.2 Initial Reset To initialize the S1C63466 circuits, initial reset must be executed. There are two ways of doing this. (1) External initial reset by the RESET terminal (2) External initial reset by simultaneous low input to terminals K00–K03 (mask option setting) The circuits are initialized by either (1) or (2).
Page 22 If an instruction which does not permit extended operation is used as the following instruction, the operation is not guaranteed. Therefore, do not write data to the EXT register for initialization only. Refer to the "S1C63000 Core CPU Manual" for extended addressing and usable instructions. EPSON S1C63466 TECHNICAL MANUAL...
Page 23 For setting procedure of the functions, see explanations for each of the peripheral circuits. 2.3 Test Terminal (TEST) This is the terminal used for the factory inspection of the IC. During normal operation, connect the TEST terminal to V EPSON S1C63466 TECHNICAL MANUAL...
Page 24 The core CPU can linearly access the program space up to step FFFFH from step 0000H, however, the program area of the S1C63466 is step 0000H to step 3FFFH. The program start address after initial reset is assigned to step 0110H. The non-maskable interrupt (NMI) vector and hardware interrupt vectors are allocated to step 0100H and steps 0104H–010EH, respectively.
Page 25 2,048 words × 4 bits. The data ROM is assigned to addresses 8000H to 87FFH on the data memory map, and the data can be read using the same data memory access instructions as the RAM. EPSON S1C63466 TECHNICAL MANUAL...
Page 26 IRCUITS AND PERATION The peripheral circuits of S1C63466 (timer, I/O, etc.) are interfaced with the CPU in the memory mapped I/O method. Thus, all the peripheral circuits can be controlled by accessing the I/O memory on the memory map using the memory operation instructions. The following sections explain the detailed operation of each peripheral circuit.
Page 27 R02 output port data (PTOUT=0) Fix at "1" when TOUT is used FF31H High R01 output port data High R00 output port data Remarks ∗1 Initial value at initial reset ∗2 Not set in the circuit ∗3 Constantly "0" when being read EPSON S1C63466 TECHNICAL MANUAL...
Page 28 SIF is selected FF46H ∗2 – High P11 I/O port data (ESIF=0) functions as a general-purpose register when SIF is selected ∗2 – High P10 I/O port data (ESIF=0) functions as a general-purpose register when SIF is selected EPSON S1C63466 TECHNICAL MANUAL...
Page 29 MSB first LSB first Serial I/F data input/output permutation SCPS Serial I/F clock phase selection SCPS SCS1 SCS0 –Negative polarity (mask option) FF71H [SCS1, 0] –Positive polarity (mask option) Clock Slave SCS1 Serial I/F [SCS1, 0] SCS0 clock mode selection Clock OSC1/2 OSC1 EPSON S1C63466 TECHNICAL MANUAL...
Page 30 RLD05 RLD04 RLD13 RLD13 RLD12 RLD11 RLD10 RLD12 Programmable timer 1 reload data (low-order 4 bits) FFC6H RLD11 RLD10 RLD17 RLD17 RLD16 RLD15 RLD14 RLD16 Programmable timer 1 reload data (high-order 4 bits) FFC7H RLD15 RLD14 EPSON S1C63466 TECHNICAL MANUAL...
Page 31 Interrupt factor flag (Clock timer 32 Hz) ∗3 ∗2 – Unused ISW1 ISW10 ∗3 ∗2 – Unused FFF7H ISW1 Interrupt factor flag (Stopwatch timer 1 Hz) ISW10 Reset Invalid Interrupt factor flag (Stopwatch timer 10 Hz) EPSON S1C63466 TECHNICAL MANUAL...
Page 32 4.2.1 Configuration of watchdog timer The S1C63466 has a built-in watchdog timer that operates with a 256 Hz divided clock from the OSC1 as the source clock. The watchdog timer starts operating after initial reset, however, it can be stopped by the software.
Page 33 (1) When the watchdog timer is being used, the software must reset it within 3-second cycles. (2) Because the watchdog timer is set in operation state by initial reset, set the watchdog timer to disabled state (not used) before generating an interrupt (NMI) if it is not used. EPSON S1C63466 TECHNICAL MANUAL...
Page 34 4.3.1 Configuration of oscillation circuit The S1C63466 has two oscillation circuits (OSC1 and OSC3). OSC1 is either a crystal or a CR oscillation circuit that supplies the operating clock to the CPU and peripheral circuits. OSC3 is either a CR or a ceramic oscillation circuit.
Page 35 (sound quality). 4.3.3 OSC3 oscillation circuit The S1C63466 has built-in the OSC3 oscillation circuit that generates the CPU's sub-clock (Max. 4 MHz) for high speed operation and the source clock for peripheral circuits needing a high speed clock (pro- grammable timer, FOUT output). The mask option enables selection of either the CR or ceramic oscilla- tion circuit.
Page 36 OSC3 operation: = 2.2 V Since the S1C63466 fixes the V voltage value at 2.2 V when the CR oscillation circuit is selected as the OSC1 oscillation circuit by mask option, it is not necessary to switch the operating voltage V software (VDC register).
Page 37 OSC3 is not performed. When the CR oscillation circuit has been selected as the OSC1 oscillation circuit by mask option, setting VDC to "0" makes no difference. At initial reset, this register is set to "0". EPSON S1C63466 TECHNICAL MANUAL...
Page 38 V using the VDC register and the V voltage is fixed at 2.2 V. The V level does not change even if any data is written to the VDC register. EPSON S1C63466 TECHNICAL MANUAL...
Page 39 4.4 Input Ports (K00–K03 and K10–K13) 4.4.1 Configuration of input ports The S1C63466 has eight bits general-purpose input ports. Each of the input port terminals (K00–K03, K10–K13) provides internal pull-up resistor. Pull-up resistor can be selected for each bit with the mask option.
Page 40 When "Gate direct" is selected, take care that the floating status does not occur for the input. Select "With pull-up resistor" for input ports that are not being used. When using the QFP5-128pin package, "With pull-up resistor" option should be chosen for the K12 input port. EPSON S1C63466 TECHNICAL MANUAL...
Page 41 The reading is "1" when the terminal voltage of the eight bits of the input ports (K00–K03, K10–K13) goes high (V ), and "0" when the voltage goes low (V These bits are dedicated for reading, so writing cannot be done. EPSON S1C63466 TECHNICAL MANUAL...
Page 42 RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state. At initial reset, these flags are set to "0". EPSON S1C63466 TECHNICAL MANUAL...
Page 43 "1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state. EPSON S1C63466 TECHNICAL MANUAL...
Page 44 (R00–R03, R10–R13 and R20–R23) 4.5.1 Configuration of output ports The S1C63466 has 12 bits general output ports. Output specifications of the output ports can be selected individually with the mask option. Two kinds of output specifications are available: complementary output and N-channel open drain output.
Page 45 R02 and R03 registers when the special output has been selected. • Be aware that the output terminal shifts into high impedance status when "1" is written to the high impedance control register (R02HIZ, R03HIZ). EPSON S1C63466 TECHNICAL MANUAL...
Page 46 Note: A hazard may occur when the FOUT signal is turned ON and OFF. Figure 4.5.4.3 shows the output waveform of the FOUT signal. R03HIZ register Fix at "0" R03 register Fix at "1" FOUTE register "0" "1" "0" FOUT output Fig. 4.5.4.3 Output waveform of FOUT signal EPSON S1C63466 TECHNICAL MANUAL...
Page 47 When "1" is written, it shifts into high impedance status. When the output ports R02 and R03 are used for special output (TOUT, FOUT), fix the R02HIZ register and the R03HIZ register at "0" (data output). At initial reset, these registers are set to "0". EPSON S1C63466 TECHNICAL MANUAL...
Page 48 "0", the TOUT signal is output from the R02 terminal. When "0" is written, the R02 termi- nal goes high (V When using the R02 output port for DC output, fix this register at "0". At initial reset, this register is set to "0". EPSON S1C63466 TECHNICAL MANUAL...
Page 49 (2) A hazard may occur when the FOUT signal and the TOUT signal are turned ON and OFF. (3) When f is selected for the FOUT signal frequency, it is necessary to control the OSC3 oscillation OSC3 circuit before output. Refer to Section 4.3, "Oscillation Circuit", for the control and notes. EPSON S1C63466 TECHNICAL MANUAL...
Page 50 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) 4.6 I/O Ports (P00–P03, P10–P13 and P20–P23) 4.6.1 Configuration of I/O ports The S1C63466 has 12 bits general-purpose I/O ports. Figure 4.6.1.1 shows the configuration of the I/O port. Pull-up control register (PUL)
Page 51 I/O control. (See Table 4.6.1.1.) 4.6.4 Pull-up during input mode A pull-up resistor that operates during the input mode is built into each I/O port of the S1C63466. Mask option can set the use or non-use of this pull-up.
Page 52 When 1/17 duty is selected CL output (P22 terminal) FR output (P23 terminal) When 1/16 duty is selected CL output (P22 terminal) FR output (P23 terminal) When 1/8 duty is selected Fig. 4.6.5.1 Output waveforms of CL and FR signals EPSON S1C63466 TECHNICAL MANUAL...
Page 53 CL output is selected ∗2 P21 I/O port data – High ∗2 P20 I/O port data – High *1 Initial value at initial reset *2 Not set in the circuit *3 Constantly "0" when being read EPSON S1C63466 TECHNICAL MANUAL...
Page 54 In the slave mode, all the P10–P13 ports are set to the serial interface input/output port. In the master mode, P10–P12 are set to the serial interface input/output port and P13 can be used as the I/O port. At initial reset, this register is set to "0". EPSON S1C63466 TECHNICAL MANUAL...
Page 55 At initial reset, these registers are all set to "0", so the I/O ports are in the input mode. The I/O control registers of the port, which are set for the special output (P22, P23) or input/output of the serial interface (P10–P12 or P10–P13), become general-purpose registers that do not affect the input/ output. EPSON S1C63466 TECHNICAL MANUAL...
Page 56 C: terminal capacitance 5 pF + parasitic capacitance ? pF R: pull-up resistance 330 kΩ (2) When special output (CL, FR) has been selected, a hazard may occur when the signal is turned ON or OFF. EPSON S1C63466 TECHNICAL MANUAL...
Page 57 4.7 LCD Driver (COM0–COM16, SEG0–SEG59) 4.7.1 Configuration of LCD driver The S1C63466 has 17 common terminals (COM0–COM16) and 60 segment terminals (SEG0–SEG59), so that it can drive a dot matrix type LCD with a maximum of 1,020 (60 × 17) dots.
Page 58 ALOFF, ALON (all ON) has priority over the ALOFF (all OFF). (2) Switching of drive duty In the S1C63466, the drive duty can be set to 1/17, 1/16 or 1/8 by the software. This setting is done using the LDUTY1 and LDUTY0 registers as shown in Table 4.7.4.1.
Page 59 ..1/17 Frame signal 32 Hz ∗ ∗ When f = 32.768 kHz OSC1 C2 ( COM0 C2 ( COM1 C2 ( COM2 C2 ( SEG0 C2 ( SEG1 Fig. 4.7.4.1 Drive waveform for 1/4 bias EPSON S1C63466 TECHNICAL MANUAL...
Page 60 1/16 ..1/17 Frame signal 32 Hz ∗ ∗ When f = 32.768 kHz OSC1 COM0 COM1 COM2 SEG0 SEG1 Fig. 4.7.4.2 Drive waveform for 1/5 bias EPSON S1C63466 TECHNICAL MANUAL...
Page 61 F107H ..F177H COM6 COM7 Unused F200H F202H F204H F206H ..F276H (b) When 1/8 duty is selected Fig. 4.7.5.1 Correspondence between display memory and LCD dot matrix EPSON S1C63466 TECHNICAL MANUAL...
Page 62 Note: When a program that access no memory mounted area (F078H–F0FFH, F178H–F1FFH, F201H, F203H, · · ·, F277H) is made, the operation is not guaranteed. 4.7.6 LCD contrast adjustment In the S1C63466, the LCD contrast can be adjusted by the software. It is realized by controlling the voltages V and V output from the LCD system voltage circuit.
Page 63 It takes about 100 msec for the LCD drive voltage to stabilize after starting up the LCD system voltage circuit by writing "1" to the LPWR register. At initial reset, this register is set to "0". When "0" is written: EPSON S1C63466 TECHNICAL MANUAL...
Page 64 By writing "1" to the ALOFF register, all the LCD dots goes OFF, and when "0" is written, it returns to normal display. This function outputs an OFF waveform to the SEG terminals, and does not affect the content of the display memory. At initial reset, this register is set to "1". EPSON S1C63466 TECHNICAL MANUAL...
Page 65 (2) Because at initial reset, the contents of display memory and LC3–LC0 (LCD contrast) are undefined, there is need to initialize by the software. Furthermore, take care of the registers LPWR and ALOFF because these are set so that the display goes OFF. EPSON S1C63466 TECHNICAL MANUAL...
Page 66 4.8 Clock Timer 4.8.1 Configuration of clock timer The S1C63466 has a built-in clock timer that uses OSC1 (crystal oscillator) as the source oscillator. The clock timer is configured of an 8-bit binary counter that serves as the input clock, f...
Page 67 (EIT0, EIT1, EIT2, EIT3). However, regardless of the interrupt mask register setting, the interrupt factor flag is set to "1" at the falling edge of the corresponding signal. EPSON S1C63466 TECHNICAL MANUAL...
Page 68 The clock timer is reset by writing "1" to TMRST. When the clock timer is reset in the RUN status, opera- tion restarts immediately. Also, in the STOP status the reset data is maintained. No operation results when "0" is written to TMRST. This bit is write-only, and so is always "0" at reading. EPSON S1C63466 TECHNICAL MANUAL...
Page 69 RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state. At initial reset, these flags are set to "0". EPSON S1C63466 TECHNICAL MANUAL...
Page 70 (3) When the CR oscillation circuit is selected as the OSC1 oscillation circuit by mask option, the frequen- cies and times differ from the values described in this section because the oscillation frequency will be 60 kHz (Typ.). Therefore, the clock timer can not be used for the clock function. EPSON S1C63466 TECHNICAL MANUAL...
Page 71 4.9 Stopwatch Timer 4.9.1 Configuration of stopwatch timer The S1C63466 has 1/100 sec unit and 1/10 sec unit stopwatch timer built-in. The stopwatch timer is configured with a 2 levels 4-bit BCD counter which has an input clock approximating 100 Hz signal (signal divided from OSC1 to the closest 100 Hz) and data can be read in units of 4 bits by software.
Page 72 The respective interrupts can be masked separately using the interrupt mask registers (EISW10 and EISW1). However, regardless of the setting of the interrupt mask registers, the interrupt factor flags are set to "1" by the overflow of their corresponding counters. EPSON S1C63466 TECHNICAL MANUAL...
Page 73 In the STOP status, the timer data is maintained until the next RUN status or the timer is reset. Also, when the STOP status changes to the RUN status, the data that is maintained can be used for resuming the count. EPSON S1C63466 TECHNICAL MANUAL...
Page 74 (3) When the CR oscillation circuit is selected as the OSC1 oscillation circuit by mask option, the frequen- cies and times differ from the values described in this section because the oscillation frequency will be 60 kHz (Typ.). Therefore, this timer can not be used for the stopwatch function. EPSON S1C63466 TECHNICAL MANUAL...
Page 75 4.10.1 Configuration of programmable timer The S1C63466 has two 8-bit programmable timer systems (timer 0 and timer 1) built-in. Timer 0 and timer 1 are composed of 8-bit presettable down counters and they can be used as 8-bit × 2 channel programmable timers.
Page 76 PTRUN0 (1) PTRST0 (1) RLD00–07 (10–17) Input clock PTD07 (17) PTD06 (16) PTD05 (15) PTD04 (14) PTD03 (13) PTD02 (12) PTD01 (11) PTD00 (10) Preset Reload & Interrupt generation Fig. 4.10.2.1 Basic operation timing of down counter EPSON S1C63466 TECHNICAL MANUAL...
Page 77 2,048 Hz* signal after changing the input level of the K13 input port terminal. Consequently, the pulse width of noise that can reliably be rejected is 0.48 msec* or less. (∗: f = 32.768 kHz). OSC1 Figure 4.10.3.2 shows the count down timing with noise rejecter. EPSON S1C63466 TECHNICAL MANUAL...
Page 78 By writing "1" to the register PTRUN0 (timer 0) or PTRUN1 (timer 1), the prescaler inputs the source clock and outputs the clock divided by the selected division ratio. The counter starts counting down by inputting the clock. EPSON S1C63466 TECHNICAL MANUAL...
Page 79 ON and OFF by setting the register. Figure 4.10.6.3 shows the output waveform of the TOUT signal. R02HIZ register Fix at "0" R02 register Fix at "1" PTOUT register "0" "1" "0" TOUT output Fig. 4.10.6.3 Output waveform of the TOUT signal EPSON S1C63466 TECHNICAL MANUAL...
Page 80 Oscillation frequency (OSC1/OSC3) bps: Transfer rate (00H can be set to RLD1X) Be aware that the maximum clock frequency for the serial interface is limited to 1 MHz when OSC3 is used as the clock source. EPSON S1C63466 TECHNICAL MANUAL...
Page 81 Unused FFF2H IPT1 Interrupt factor flag (Programmable timer 1) IPT0 Reset Invalid Interrupt factor flag (Programmable timer 0) *1 Initial value at initial reset *2 Not set in the circuit *3 Constantly "0" when being read EPSON S1C63466 TECHNICAL MANUAL...
Page 82 The counter mode for timer 0 is selected from either the event counter mode or timer mode. When "1" is written to the EVCNT register, the event counter mode is selected and when "0" is written, the timer mode is selected. At initial reset, this register is set to "0". EPSON S1C63466 TECHNICAL MANUAL...
Page 83 Since the high-order 4 bits are held by reading the low-order 4 bits, be sure to read the low-order 4 bits first. Since these latches are exclusively for reading, the writing operation is invalid. At initial reset, these counter data are set to "00H". EPSON S1C63466 TECHNICAL MANUAL...
Page 84 R02 and when "0" is written, the terminal goes to a high ) level. However, the data register R02 must always be "1" and the high impedance control register R02HIZ must always be "0" (data output state). At initial reset, this register is set to "0". EPSON S1C63466 TECHNICAL MANUAL...
Page 85 RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state. At initial reset, these flags are set to "0". EPSON S1C63466 TECHNICAL MANUAL...
Page 86 "1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state. EPSON S1C63466 TECHNICAL MANUAL...
Page 87 The synchronous clock for serial data input/output may be set by selecting by software any one of three types of master mode (internal clock mode: when the S1C63466 is to be the master for serial input/ output) and a type of slave mode (external clock mode: when the S1C63466 is to be the slave for serial input/output).
Page 88 4.11.3 Master mode and slave mode of serial interface The serial interface of the S1C63466 has two types of operation mode: master mode and slave mode. The master mode uses an internal clock as the synchronous clock for the built-in shift register, and outputs this internal clock from the SCLK (P12) terminal to control the external (slave side) serial device.
Page 89 (1) Serial data output procedure and interrupt The S1C63466 serial interface is capable of outputting parallel data as serial data, in units of 8 bits. By setting the parallel data to the data registers SD0–SD3 (FF72H) and SD4–SD7 (FF73H) and writing "1"...
Page 90 (2) Serial data input procedure and interrupt The S1C63466 serial interface is capable of inputting serial data as parallel data, in units of 8 bits. The serial data is input from the SIN (P10) terminal, synchronizes with the synchronous clock, and is sequentially read in the 8-bit shift register.
Page 91 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) (5) Timing chart The S1C63466 serial interface timing charts are shown in Figures 4.11.4.2 and 4.11.4.3. SCTRG (W) SCTRG (R) SCLK 8-bit shift register SOUT ISIF SRDY (Slave mode) (a) When SCPS = "1"...
Page 92 At initial reset, this register is set to "0". Note: After setting ESIF to "1", wait at least 10 µsec before starting actual data transfer since a hazard may be generated from the P12 (SCLK) terminal when ESIF is set to "1". EPSON S1C63466 TECHNICAL MANUAL...
Page 93 The input data fetch timing may be selected but output timing for output data is fixed at the falling edge of SCLK (when negative polarity is selected) or at the rising edge of SCLK (when positive polarity is selected). At initial reset, this register is set to "0". EPSON S1C63466 TECHNICAL MANUAL...
Page 94 ) level bit into "0", and is loaded to these registers. Perform data reading only while the serial interface is not running (i.e., the synchronous clock is neither being input or output). At initial reset, these registers are undefined. EPSON S1C63466 TECHNICAL MANUAL...
Page 95 "1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state. EPSON S1C63466 TECHNICAL MANUAL...
Page 96 4.12 Sound Generator 4.12.1 Configuration of sound generator The S1C63466 has a built-in sound generator for generating buzzer signals. Hence, generated buzzer signals (BZ) can be output from the BZ terminal. Aside permitting the respective setting of the buzzer signal frequency and sound level to 8 stages, it permits the adding of a digital envelope by means of duty ratio control.
Page 97 Conversely, when BDTY0–BDTY2 have all been set to "1", the duty ratio becomes minimum and the sound level also becomes minimum. The duty ratio that can be set is different depending on the frequency that has been set, so see Table 4.12.4.2. EPSON S1C63466 TECHNICAL MANUAL...
Page 98 BZFQ0–2 ENON ENRST ENRTM BZ signal Level 1 (Max.) duty ratio 8 (Min.) = 62.5 msec = 125 msec –4 –4 = 62.5 msec = 125 msec 02–07 12–17 Fig. 4.12.5.1 Timing chart for digital envelope EPSON S1C63466 TECHNICAL MANUAL...
Page 99 One-shot output is invalid during normal buzzer output (during BZE = "1"). Figure 4.12.6.1 shows timing chart for one-shot output. 256 Hz SHTPW BZSHT (W) BZSHT (R) BZSTP BZ output (Negative polarity) BZ output (Positive polarity) Fig. 4.12.6.1 Timing chart for one-shot output EPSON S1C63466 TECHNICAL MANUAL...
Page 100 Buzzer frequency (Hz) 4096.0 3276.8 2730.7 2340.6 2048.0 1638.4 1365.3 1170.3 Select the buzzer frequency from among the above 8 types that have divided the oscillation clock. At initial reset, this register is set to "0". EPSON S1C63466 TECHNICAL MANUAL...
Page 101 When "1" has been written in ENRTM, it becomes 125 msec (8 Hz) units and when "0" has been written, it becomes 62.5 msec (16 Hz) units. At initial reset, this register is set to "0". EPSON S1C63466 TECHNICAL MANUAL...
Page 102 (3) The buzzer signal is generated by dividing the OSC1 oscillation clock. Since the frequencies and times that are described in this section are the values in the case of crystal oscillation (32.768 kHz, Typ.), they differ when CR oscillation (60 kHz, Typ.) is selected. EPSON S1C63466 TECHNICAL MANUAL...
Page 103 4.13.1 Configuration of SVD circuit The S1C63466 has a built-in SVD (supply voltage detection) circuit, so that the software can find when the source voltage lowers. It is possible to check an external voltage drop, other than the supply voltage, by mask option.
Page 104 When "1" is read: Supply voltage (V –V ) < Criteria voltage Writing: Invalid The result of supply voltage detection at time of SVDON is set to "0" can be read from this latch. At initial reset, SVDDT is set to "0". EPSON S1C63466 TECHNICAL MANUAL...
Page 105 SVD detection result, follow the programming sequence below. 1. Set SVDON to "1" 2. Maintain for 100 µsec minimum 3. Set SVDON to "0" 4. Read SVDDT (2) The SVD circuit should normally be turned OFF because SVD operation increase current consump- tion. EPSON S1C63466 TECHNICAL MANUAL...
Page 106 NMI are masked and interrupts cannot be accepted until the other one is set. <HALT> The S1C63466 has HALT functions that considerably reduce the current consumption when it is not necessary. The CPU enters HALT status when the HALT instruction is executed.
Page 107 KCP10 SIK10 KCP11 Interrupt factor flag SIK11 Interrupt mask register EIK1 KCP12 Input comparison register SIK12 Interrupt selection register KCP13 SIK13 EIT3 EIT2 EIT1 EIT0 ISW1 EISW1 ISW10 EISW10 Fig. 4.14.1 Configuration of the interrupt circuit EPSON S1C63466 TECHNICAL MANUAL...
Page 108 "1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state. EPSON S1C63466 TECHNICAL MANUAL...
Page 109 Watchdog timer High 0104H Programmable timer 0106H Serial interface 0108H K00–K03 input 010AH K10–K13 input 010CH Clock timer 010EH Stopwatch timer The four low-order bits of the program counter are indirectly addressed through the interrupt request. EPSON S1C63466 TECHNICAL MANUAL...
Page 110 Mask Interrupt mask register (Stopwatch timer 1 Hz) EISW10 Enable Mask Interrupt mask register (Stopwatch timer 10 Hz) *1 Initial value at initial reset *2 Not set in the circuit *3 Constantly "0" when being read EPSON S1C63466 TECHNICAL MANUAL...
Page 111 EIT3–EIT0: Interrupt mask registers (FFE6H) IT3–IT0: Interrupt factor flags (FFF6H) Refer to Section 4.8, "Clock Timer". EISW1, EISW10: Interrupt mask registers (FFE7H•D1, D0) ISW1, ISW10: Interrupt factor flags (FFF7H•D1, D0) Refer to Section 4.9, "Stopwatch Timer". EPSON S1C63466 TECHNICAL MANUAL...
Page 112 Further, when re-setting the stack pointer, the SP1 and SP2 must be set as a pair. When one of them is set, all the interrupts including NMI are masked and interrupts cannot be accepted until the other one is set. EPSON S1C63466 TECHNICAL MANUAL...
Page 113 UMMARY OF OTES 5.1 Notes for Low Current Consumption The S1C63466 contains control registers for each of the circuits so that current consumption can be reduced. These control registers reduce the current consumption through programs that operate the circuits at the minimum levels.
Page 114 0000H to 00FFH. Therefore, pay attention to the SP1 value because it may be set to 0200H or more exceeding the 4-bit/16-bit accessible range in the S1C63466 or it may be set to 00FFH or less. Memory accesses except for stack operations by SP1 are 4-bit data access.
Page 115 (2) When the CR oscillation circuit is selected as the OSC1 oscillation circuit by mask option, the frequen- cies and times differ from the values described in this section because the oscillation frequency will be 60 kHz (Typ.). Therefore, the clock timer can not be used for the clock function. EPSON S1C63466 TECHNICAL MANUAL...
Page 116 SD0–SD7. (4) Be aware that the maximum clock frequency for the serial interface is limited to 1 MHz when OSC3 is used as the clock source of the programmable timer or in the slave mode. EPSON S1C63466 TECHNICAL MANUAL...
Page 117 Further, when re-setting the stack pointer, the SP1 and SP2 must be set as a pair. When one of them is set, all the interrupts including NMI are masked and interrupts cannot be accepted until the other one is set. EPSON S1C63466 TECHNICAL MANUAL...
Page 118 (1) Design the product and implement the IC on the board so that it is shielded from visible radiation in actual use. (2) The inspection process of the product needs an environment that shields the IC from visible radiation. (3) As well as the face of the IC, shield the back and side too. EPSON S1C63466 TECHNICAL MANUAL...
Page 119 Unit Supply voltage OSC3 oscillation OFF OSC1 CR oscillation OSC3 oscillation ON Oscillation frequency Crystal oscillation – 32.768 – OSC1 CR oscillation CR oscillation 1,800 2,250 OSC3 Ceramic oscillation 4,100 SVD terminal input voltage =0V, SVD≤V EPSON S1C63466 TECHNICAL MANUAL...
Page 120 High level output current (2) =0.9·V Low level output current (1) =0.1·V R00–03, R10–13, R20–23 P00–03, P10–13, P20–23 Low level output current (2) =0.1·V µA Common output current -0.05V COM0–16 µA +0.05V µA Segment output current -0.05V SEG0–59 µA +0.05V EPSON S1C63466 TECHNICAL MANUAL...
Page 121 LC0–3="13" 2.34 LC0–3="14" 2.37 LC0–3="15" 2.40 Connect 1 MΩ load resistor between V and V 3/2·V 3/2·V ×0.95 (without panel load) Connect 1 MΩ load resistor between V and V 2·V 2·V ×0.95 (without panel load) EPSON S1C63466 TECHNICAL MANUAL...
Page 122 ∗1 Without panel load. The SVD circuit is OFF. ∗2 VDC = "0" ∗3 OSCC = "0" ∗4 Please input the voltage, which is within the range between V and V , into the SVD terminal. EPSON S1C63466 TECHNICAL MANUAL...
Page 123 Unless otherwise specified: =3.0V, V =0V, R =47kΩ, Ta=-20 to 70°C Item Symbol Condition Min. Typ. Max. Unit Oscillation frequency dispersion 1,800kHz OSC3 Oscillation start voltage Vsta Oscillation start time =2.2 to 6.4V Oscillation stop voltage Vstp EPSON S1C63466 TECHNICAL MANUAL...
Page 124 2.2M = 2.2 to 6.4 V 2.1M = 0 V Ta = 25°C 2.0M Typ. value 1.9M 1.8M 1.7M 1.6M 1.5M 1.4M 1.3M 1.2M 1.1M 100k 110k 120k Resistor value for CR oscillation R [Ω] EPSON S1C63466 TECHNICAL MANUAL...
Page 125 Transmitting data output delay time Receiving data input set-up time Receiving data input hold time Note that the maximum clock frequency is limited to 1 MHz. <Master mode> SCLK OUT SOUT <Slave mode> SCLK IN SOUT EPSON S1C63466 TECHNICAL MANUAL...
Page 126 Note: When the OSC1 oscillation circuit has been selected as the CR oscillation circuit, it is not neces- sary to set the VDC register. Whether the VDC register value is "1" or "0" does not matter. EPSON S1C63466 TECHNICAL MANUAL...
Page 127 CHAPTER 8: PACKAGE CHAPTER ACKAGE 8.1 Plastic Package QFP8-144pin (Unit: mm) ±0.4 31.2 ±0.1 INDEX ±0.1 0.65 ±0.05 0.15 0° 10° ±0.2 The dimensions are subject to change without notice. EPSON S1C63466 TECHNICAL MANUAL...
Page 128 CHAPTER 8: PACKAGE QFP17-144pin (Unit: mm) ±0.4 ±0.1 INDEX +0.1 –0.05 ±0.05 0.15 0° 10° ±0.2 The dimensions are subject to change without notice. EPSON S1C63466 TECHNICAL MANUAL...
Page 129 CHAPTER 8: PACKAGE QFP5-128pin (Unit: mm) ±0.4 23.6 ±0.1 INDEX ±0.05 ±0.05 0.15 0° 10° ±0.2 The dimensions are subject to change without notice. EPSON S1C63466 TECHNICAL MANUAL...
Page 130 CHAPTER 8: PACKAGE 8.2 Ceramic Package for Test Samples QFP8-144pin (Unit: mm) ±0.30 36.93 ±0.28 28.00 ±0.05 ±0.05 0.65 0.30 1.20 Typ. EPSON S1C63466 TECHNICAL MANUAL...
Page 131 CHAPTER 8: PACKAGE QFP17-144pin (Unit: mm) ±0.25 22.00 ±0.19 19.20 0.50 0.20 ±0.20 0.50 EPSON S1C63466 TECHNICAL MANUAL...
Page 132 CHAPTER 8: PACKAGE QFP5-128pin (Unit: mm) ±0.30 23.90 ±0.18 20.00 CERAMIC GLASS ±0.20 0.80 EPSON S1C63466 TECHNICAL MANUAL...
Page 133 CHAPTER 9: PAD LAYOUT CHAPTER AYOUT 9.1 Diagram of Pad Layout Die No. (0, 0) 5.44 mm Chip thickness: 400 µm Pad opening: 100 µm EPSON S1C63466 TECHNICAL MANUAL...
Page 134 2445 SEG50 -2595 -1751 SEG17 1755 -2445 TEST 2595 2162 -2151 2445 SEG49 -2595 -1881 SEG16 1885 -2445 2595 2292 N.C. -2281 2445 SEG48 -2595 -2011 SEG15 2015 -2445 N.C. 2595 2442 N.C. : No Connection EPSON S1C63466 TECHNICAL MANUAL...
Page 135 These LEDs correspond one-to-one to the registers listed below. The LED lights when the data is logic "1" and goes out when the data is logic "0". VDC, OSCC, CLKCHG, SVDS0–3 ∗ , SVDON ∗ , LPWR, VCCHG ∗ SVDS0–3, SVDON: Used for the S1C63404/458/466/P466 EPSON S1C63466 TECHNICAL MANUAL...
Page 136 These pins allow you to monitor the clock waveform from the CR oscillation circuit with an oscillo- scope. Note that these pins always output a signal waveform whether or not the oscillation circuit is operating. RESET OSC3 monitor pin (red) OSC1 monitor pin (red) GND pin (black) EPSON S1C63466 TECHNICAL MANUAL...
Page 137 This control allows fine adjustment of the LCD drive voltage when the internal LCD power supply is selected by mask option. Note, however, that only the LCD contrast register can adjust the LCD drive voltage in the actual IC. EPSON S1C63466 TECHNICAL MANUAL...
Page 138 (80-pin/40-pin × 2, flat type). Take care when handling the connectors, since they conduct electrical power (V = +3.3 V). mark I/O connection cable CN1-1 (40-pin) CN1-2 (40-pin) To target board Fig. A.2.1 Connecting the S5U1C63000P to the target system EPSON S1C63466 TECHNICAL MANUAL...
Page 139 C2 *2 Cannot be connected C3 *2 Cannot be connected C4 *2 Cannot be connected C5 *2 Cannot be connected RESET ∗1: Can be used only for the S1C63404/458/466/P466 ∗2: Can be used only for the S1C63404/454/458/466/P466 EPSON S1C63466 TECHNICAL MANUAL...
Page 140 LCD power supply on/off circuit (LPWR) g) LCD constant-voltage change circuit (VCCHG) <Those that can only be counteracted by system or software> h) Current consumed by the internal pull-up resistors i) Input ports in a floating state EPSON S1C63466 TECHNICAL MANUAL...
Page 141 - Since the usable operating frequency range depends on the device's internal operating voltage, consult the technical manual for the S1C63404/454/455/458/466/P466 to ensure that the device will not be operated with an inappropriate combination of the operating frequency and the internal power supply. EPSON S1C63466 TECHNICAL MANUAL...
Page 142 - Do not change the value of the LPAGE bit (FF61H•D0) initialized to 0 as rewriting cause a malfunc- tion. ∗1: Applied when this board is used for the S1C63404/458/466/P466 ∗2: Applied when this board is used for the S1C63454/455 ∗3: Applied when this board is used for the S1C63455 EPSON S1C63466 TECHNICAL MANUAL...
Page 143 Central Phone: +852-2585-4600 Fax: +852-2827-4346 101 Virginia Street, Suite 290 Telex: 65542 EPSCO HX Crystal Lake, IL 60014, U.S.A. EPSON TAIWAN TECHNOLOGY & TRADING LTD. Phone: +1-815-455-7630 Fax: +1-815-455-7633 10F, No. 287, Nanking East Road, Sec. 3 Northeast Taipei 301 Edgewater Place, Suite 120...
Page 144 S1C63466 Technical Manual ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epsondevice.com First issue July, 1998 Printed October, 2001 in Japan...

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